LT3971/LT3971-3.3/LT3971-5 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.5V Start-Up and DropoutFeedback Regulation VoltageMinimum Input Voltage to Switch 1.6 5 VIN 1.2 4 /DIV 0.8 3 1V VOUT INPUT VOLTAGE (V) FEEDBACK VOLTAGE (V) 0.4 2 0 1 0.5s/DIV 3971 G34 2 2.5 3 3.5 4 4.5 5 –55 –25 5 35 65 95 125 155 800kHz INPUT VOLTAGE (V) TEMPERATURE (°C) 10Ω LOAD 3971 G35 3971 G36 PIN FUNCTIONS (DFN, MSE10/MSE16)BD (Pin 1/Pin 1): This pin connects to the anode of the SS (Pin 7/Pin 12): A capacitor is tied between SS and boost diode. The BD pin is normally connected to the output. ground to slowly ramp up the peak current limit of the BOOST (Pin 2/Pin 3): This pin is used to provide a drive LT3971 on start-up. The soft-start capacitor is only actively voltage, higher than the input voltage, to the internal bipolar discharged when EN is low. The SS pin is released when NPN power switch. the EN pin goes high. Float this pin to disable soft-start. For applications with input voltages above 25V, add a 100k SW (Pin 3/Pin 5): The SW pin is the output of an internal resistor in series with the soft-start capacitor. power switch. Connect this pin to the inductor, catch diode, and boost capacitor. RT (Pin 8/Pin 13): A resistor is tied between RT and ground to set the switching frequency. VIN (Pin 4/Pin 7): The VIN pin supplies current to the LT3971’s internal circuitry and to the internal power switch. PG (Pin 9/Pin 14): The PG pin is the open-drain output of This pin must be locally bypassed. an internal comparator. PGOOD remains low until the FB pin is within 9% of the final regulation voltage. PGOOD is EN (Pin 5/Pin 8): The part is in shutdown when this pin valid when the LT3971 is enabled and VIN is above 4.3V. is low and active when this pin is high. The hysteretic threshold voltage is 1.005V going up and 0.975V going SYNC (Pin 10/Pin 15): This is the external clock synchro- down. The EN threshold is only accurate when V nization input. Ground this pin for low ripple Burst Mode IN is above 4.3V. If V operation at low output loads. Tie to a clock source for IN is lower than 4.2V, ground EN to place the part in shutdown. Tie to V synchronization, which will include pulse-skipping at low IN if shutdown feature is not used. output loads. When in pulse-skipping mode, quiescent FB (Pin 6, LT3971 Only/Pins 9, 10): The LT3971 regulates current increases to 1.5mA. the FB pin to 1.19V. Connect the feedback resistor divider tap to this pin. Also, connect a phase lead capacitor between GND (Exposed Pad Pin 11/Pin 16, Exposed Pad Pin 17): FB and V Ground. The exposed pad must be soldered to PCB. OUT. Typically this capacitor is 10pF. VNC (None/Pins 2, 4, 6, 11): No Connect. These pins OUT (Pin 6, LT3971-3.3 and LT3971-5 Only): The LT3971-3.3 and LT3971-5 regulate the V are not connected to internal circuitry. Float these pins OUT pin to 3.3V and 5V respectively. This pin connects to the internal 10MΩ to achieve FMEA fault tolerance. (See Fault Tolerance of feedback divider that programs the fixed output voltage. MS16E Package section.) 3971fd 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts