Datasheet LT8610 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 42V, 2.5A Synchronous Step-Down Regulator with 2.5μA Quiescent Current |
| Páginas / Página | 22 / 9 — PIN FUNCTIONS BIAS (Pin 14):. FB (Pin 16):. GND (Exposed Pad Pin 17):. PG … |
| Formato / tamaño de archivo | PDF / 308 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS BIAS (Pin 14):. FB (Pin 16):. GND (Exposed Pad Pin 17):. PG (Pin 15):. BLOCK DIAGRAM
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LT8610
PIN FUNCTIONS BIAS (Pin 14):
The internal regulator will draw current from
FB (Pin 16):
The LT8610 regulates the FB pin to 0.970V. BIAS instead of VIN when BIAS is tied to a voltage higher Connect the feedback resistor divider tap to this pin. Also, than 3.1V. For output voltages of 3.3V and above this pin connect a phase lead capacitor between FB and VOUT. should be tied to VOUT. If this pin is tied to a supply other Typically, this capacitor is 4.7pF to 10pF. than VOUT use a 1µF local bypass capacitor on this pin.
GND (Exposed Pad Pin 17):
Ground. The exposed pad
PG (Pin 15):
The PG pin is the open-drain output of an must be connected to the negative terminal of the input internal comparator. PG remains low until the FB pin is capacitor and soldered to the PCB in order to lower the within ±9% of the final regulation voltage, and there are thermal resistance. no fault conditions. PG is valid when VIN is above 3.4V, regardless of EN/UV pin state.
BLOCK DIAGRAM
VIN VIN C 5, 6 IN – INTERNAL 0.97V REF + 3.4V BIAS R3 1V + REG 14 OPT EN/UV 4 – SHDN SLOPE COMP INTV R4 CC 13 OPT C OSCILLATOR VCC ERROR PG 200kHz TO 2.2MHz BST 15 ±9% AMP 12 + V C + C BURST SWITCH M1 BST V – DETECT LOGIC SW L OUT AND VOUT ANTI- 9-11 COUT SHOOT SHDN C1 R1 TSD THROUGH M2 INTVCC UVLO R2 VIN UVLO FB PGND 16 SHDN CSS 7, 8 TSD OPT 2.2µA VIN UVLO TR/SS 2 RT RT 3 SYNC 1 GND 8610 BD 17 8610fa For more information www.linear.com/LT8610 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS BIAS (Pin 14):
The internal regulator will draw current from
FB (Pin 16):
The LT8610 regulates the FB pin to 0.970V. BIAS instead of VIN when BIAS is tied to a voltage higher Connect the feedback resistor divider tap to this pin. Also, than 3.1V. For output voltages of 3.3V and above this pin connect a phase lead capacitor between FB and VOUT. should be tied to VOUT. If this pin is tied to a supply other Typically, this capacitor is 4.7pF to 10pF. than VOUT use a 1µF local bypass capacitor on this pin.
GND (Exposed Pad Pin 17):
Ground. The exposed pad
PG (Pin 15):
The PG pin is the open-drain output of an must be connected to the negative terminal of the input internal comparator. PG remains low until the FB pin is capacitor and soldered to the PCB in order to lower the within ±9% of the final regulation voltage, and there are thermal resistance. no fault conditions. PG is valid when VIN is above 3.4V, regardless of EN/UV pin state.
BLOCK DIAGRAM
VIN VIN C 5, 6 IN – INTERNAL 0.97V REF + 3.4V BIAS R3 1V + REG 14 OPT EN/UV 4 – SHDN SLOPE COMP INTV R4 CC 13 OPT C OSCILLATOR VCC ERROR PG 200kHz TO 2.2MHz BST 15 ±9% AMP 12 + V C + C BURST SWITCH M1 BST V – DETECT LOGIC SW L OUT AND VOUT ANTI- 9-11 COUT SHOOT SHDN C1 R1 TSD THROUGH M2 INTVCC UVLO R2 VIN UVLO FB PGND 16 SHDN CSS 7, 8 TSD OPT 2.2µA VIN UVLO TR/SS 2 RT RT 3 SYNC 1 GND 8610 BD 17 8610fa For more information www.linear.com/LT8610 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts