Datasheet LTC3649 (Analog Devices) - 7

LTC3649
PIN FUNCTIONS (QFN/TSSOP) PGND (Pins 1, 2, 26-28/Pins 1-5):
Ground Pins for Power
VOUT (Pin 13/Pin 16):
Output Voltage Error Amplifier Input Switch. Pin. Connect to the output of the LTC3649 voltage regulator.
VIN (Pin 3, 4/Pins 6, 7):
Input Supply Pin of the Step-
ISET (Pin 14/Pin 17):
Accurate 50µA Bias Current and Down Regulator. Positive Input to the Error Amplifier. Connect an external
RUN (Pin 5/Pin 8):
Logic Controlled RUN Input. Do not resistor from this pin to SGND to program the output leave this pin floating. Place a resistor divider from V voltage. Connecting an external capacitor from ISET to IN to GND for an accurate V ground will soft start the output voltage by reducing cur- IN undervoltage threshold. rent inrush during start-up.
SGND (Pins 6, 29/Pins 9, 29):
Signal Ground Pin of the Step-Down Regulator. The exposed pad must be soldered
ITH (Pin 15/Pin 18):
Error Amplifier Output and Switching to PCB ground for electrical connection and rated thermal Regulator Compensation Point. The current comparator’s performance. trip threshold is linearly proportional to this voltage. Tying this pin to INTVCC activates internal compensation.
MODE/SYNC (Pin 7/Pin 10):
Mode Select and Oscillator Synchronization Input of the Step-Down Regulator. Leave
EXTVCC (Pin 16/ Pin 19):
External Power Input to the MODE/SYNC floating for forced continuous mode opera- Internal Regulator. The internal regulator will draw cur- tion or tie MODE/SYNC to GND for Burst Mode operation. rent from EXTVCC instead of VIN when EXTVCC is tied to a Furthermore, connecting MODE/SYNC to an external clock voltage higher than 3.2V and VIN is above 5V. For output will synchronize the internal oscillator to the external clock voltages at or above 3.3V and less than 28V, this pin can signal and put the part in forced continuous mode. be tied to VOUT. If this pin is tied to a supply other than VOUT, locally bypass with at least a 1µF to GND.
PGOOD (Pin 8/Pin 11):
VOUT Within Regulation Indicator. PGOOD is pulled to GND when V
INTVCC (Pin 17/Pin 20):
Low Dropout Regulator. Locally PGFB is more than 0.645V or less than 0.555V. bypass with at least 2.2µF to GND.
PGDFB (Pin 9/Pin 12):
Power Good Feedback. Place a resis-
BOOST (Pin 18/Pin 21):
Boosted Floating Driver Supply tor divider from V for Internal Top Power MOSFET. Place a 0.1µF bootstrap OUT to GND to detect power good level. capacitor between BOOST and SW.
IMON (Pin 10/Pin 13):
Output Current Monitoring Pin. The current coming out of this pin is equal to 1/40,000
SW (Pins 19-25/Pins 22-28):
Switch Node Connection to of the average output current. the Inductor of the Step-Down Regulator.
VINREG (Pin 11/Pin 14):
Input Voltage Regulation Sense Input. Place a resistor divider from VIN to GND to program the level of input voltage regulation.
RT (Pin 12/Pin 15):
Oscillator Frequency Programming Pin. Connect an external resistor between 333.3k to 33.3k from RT to GND to program the frequency from 300kHz to 3MHz respectively. Since the synchronization range is limited to ±50% of the set frequency, be sure that either the external clock is within this range or RT is set to ac- commodate the external clock for proper frequency lock. 3649fb For more information www.linear.com/LTC3649 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts