Datasheet ADP2360 (Analog Devices) - 3

Data Sheet ADP2360 SPECIFICATIONS
VIN = VEN = 24 V, VOUT = 3.3 V, typical values are at TA = 25°C, and minimum/maximum limits are guaranteed for TJ = −40°C to +125°C, unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1. Parameters Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE SUPPLY RANGE VIN 4.5 60 V QUIESCENT CURRENT Sleep Mode IQ_SLEEP Between switching cycles, 12 23 µA FB > VFB_RISING Active IQ_ACTIVE During switching cycle, FB < VFB_FALLING 140 165 µA Shutdown Current IQ_SHUTDOWN VEN = 0 V, TJ = −40°C to +85°C 0.8 4 µA UNDERVOLTAGE LOCKOUT (UVLO) VIN UVLO Rising Threshold VUVLO_RISING 4.3 4.4 4.5 V VIN UVLO Falling Threshold VUVLO_FALLING 4.1 4.2 4.3 V SOFT START (SS) SS Pin Current ISS VSS = 0 V 0.75 1 1.25 µA PRECISION ENABLE LOGIC/SHUTDOWN EN Pin Voltage Range VEN 0 60 V EN Threshold Rising VEN_RISING 0.95 1 1.05 V EN Hysteresis VEN_HYS 50 mV EN Pin Leakage Current IEN_LEAKAGE VIN = VEN = 60 V 0.1 0.5 µA Shutdown Threshold VEN_SHUTDOWN 0.35 0.57 0.7 V FEEDBACK Adjustable Output Voltage Range VOUT 0.8 VIN V FB Falling Threshold VFB_FALLING Adjustable output voltage model 0.792 0.800 0.808 V Fixed 3.3 V output voltage model 3.267 3.300 3.333 V Fixed 5.0 V output voltage model 4.950 5.000 5.050 V FB Rising Threshold VFB_RISING Adjustable output voltage model 0.794 0.803 0.812 V Fixed 3.3 V output voltage model 3.284 3.317 3.349 V Fixed 5.0 V output voltage model 4.975 5.025 5.075 V FB Pin Current IFB Adjustable output voltage models 0.005 0.1 µA Fixed output voltage models 1.15 1.5 µA SWITCH (SW) PARAMETERS On Resistance Positive Metal Oxide Semiconductor (PMOS) RDSON_P ISW = 50 mA 4 8 Ω Negative Metal Oxide Semiconductor (NMOS) RDSON_N ISW = 50 mA 2 4 Ω Leakage Current PMOS VSW = 0 V 1 µA NMOS VSW = 24 V 1 µA Discharge Resistor EN = 0 V 100 kΩ INDUCTOR CURRENT LIMIT ITH Threshold Voltage VITH 0.967 1 1.018 V Peak Current Limit IPEAK RITH = 0 Ω, at power-up 126 140 154 mA RITH = open, at power-up 45 50 55 mA Minimum PMOS on Time tPMOS (MIN) ISW = 20 mA, RITH = open 35 ns POWER GOOD (PG) PG Pin Voltage Range VPG 0 60 V PG Pin Pull-Down Resistance RPG 1.0 1.5 kΩ Rising Threshold VPG_RISING Adjustable output voltage model 0.740 0.760 V Fixed 3.3 V output voltage model 3.053 3.135 V Fixed 5.0 V output voltage model 4.625 4.750 V Rev. A | Page 3 of 15 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION OVERVIEW CONTROL SCHEME 100% Duty Cycle Adjustable Peak Current Threshold (ITH) DEVICE FEATURES Fixed and Adjustable Output Models Shutdown/Precision Enable Soft Start Thermal Shutdown (TSD) Undervoltage Lockout (UVLO) Power Good APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE INPUT CAPACITOR SELECTION ESTIMATING THE SWITCHING FREQUENCY SETTING THE PEAK INDUCTOR CURRENT INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION DESIGN OPTIMIZATION RECOMMENDED COMPONENTS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE