Datasheet LT8650S (Analog Devices) - 10

link to page 15 link to page 15 LT8650S
PIN FUNCTIONS RT (Pin 1):
A resistor is tied between RT and ground to are no fault conditions. PG1 is pulled low during VIN1 set the switching frequency. UVLO, VCC UVLO, Thermal Shutdown, or when both EN/
V
UV pins are low.
IN1 (Pin 4, 5):
The VIN1 pin supplies current to the LT8650S internal circuitry and to the internal top side power switch
PG2 (Pin 15):
The PG2 pin is the open-drain output of an of channel 1. This pin must be locally bypassed. Be sure to internal comparator. PG2 remains low until the FB2 pin place the positive terminal of the input capacitor as close is within ±7.5% of the final regulation voltage, and there as possible to the VIN1 pin, and the negative capacitor are no fault conditions. PG2 is pulled low during VIN1 terminal as close as possible to the GND pins. UVLO, VCC UVLO, Thermal Shutdown, or when both EN/
V
UV pins are low.
IN2 (Pin 7, 8):
The VIN2 pin supplies current to the internal top side power switch of channel 2. This pin must be lo-
SYNC (Pin 16):
External Clock Synchronization Input. cally bypassed. Be sure to place the positive terminal of Ground this pin for low ripple Burst Mode operation at the input capacitor as close as possible to the VIN2 pin, low output loads. Apply a DC voltage of 2.8V to 4V or tie and the negative capacitor terminal as close as possible to VCC for forced continuous mode with spread spectrum to the GND pins. This input is capable of operating from modulation. Float the SYNC pin for forced continuous mode a different supply than VIN1. VIN1 must be present to run without spread spectrum modulation. When in forced con- channel 2. tinuous mode, the IQ will increase to several hundred µA.
EN/UV1 (Pin 11):
Channel 1 of the LT8650S is shut down Apply a clock source to the SYNC pin for synchronization when this pin is low and active when this pin is high. The to an external frequency. The LT8650S will be in forced hysteretic threshold voltage is 0.77V going up and 0.74V continuous mode when an external frequency is applied. going down. Tie to VIN1 if the shutdown feature is not
CLKOUT (Pin 17):
In forced continuous mode, the CLKOUT used. An external resistor divider from VIN1 can be used pin provides a 50% duty cycle square wave 90 degrees to program a VIN threshold below which channel 1 of the out of phase with channel 1. This allows synchronization LT8650S will shut down. Do not float this pin. with other regulators with up to four phases. When an
EN/UV2 (Pin 12):
Channel 2 of the LT8650S is shut down external clock is applied to the SYNC pin, the CLKOUT pin when this pin is low and active when this pin is high. The will output a waveform with the same phase, duty cycle, hysteretic threshold voltage is 0.77V going up and 0.74V and frequency as the SYNC waveform. In burst mode, going down. Tie to V the CLKOUT pin will be low. Float this pin if the CLKOUT IN2 if shutdown feature is not used. An external resistor divider from V function is not used. IN2 can be used to program a VIN threshold below which channel 2 of the LT8650S
BST2 (Pin 18):
This pin is used to provide a drive voltage, will shut down. Do not float this pin. higher than the input voltage, to the top side power switch
TEMP (Pin 13):
Temperature Output Pin. This pin outputs of channel 2. Place a 0.1µF boost capacitor as close as a voltage proportional to junction temperature. The pin is possible to the IC. 250mV for 25°C and has a slope of 9.5mV/°C. The output
SW2 (Pin 19, 20):
The SW2 pin is the output of the chan- of this pin is not valid during light output loads on both nel 2 internal power switches. Tie these pins together and channels while in Burst Mode operation. Put the LT8650S connect them to the inductor and boost capacitor. This node in forced continuous mode for the TEMP output to be valid should be kept small on the PCB for good performance. across the entire output load range. See the Applications
SW1 (Pin 22, 23):
The SW1 pin is the output of the chan- Information section for more information. nel 1 internal power switches. Tie these pins together and
PG1 (Pin 14):
The PG1 pin is the open-drain output of an connect them to the inductor and boost capacitor. This node internal comparator. PG1 remains low until the FB1 pin should be kept small on the PCB for good performance. is within ±7.5% of the final regulation voltage, and there Rev A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts