Datasheet LTC1152 (Analog Devices) - 7

LTC1152
O U U W U APPLICATI S I FOR ATIO Compensation/Bandwidth Limiting
is running from ±5V or ±3V supplies. The internal 1µA pull-up also allows pin 1 to interface with open-collector/ The LTC1152 is unity-gain stable with capacitive loads up open-drain devices or discrete transistors. to 1000pF. Larger capacitive loads can be driven by externally compensating the LTC1152. Adding 1000pF The high impedance output in shutdown allows several between COMP (pin 5) and OUT (pin 6) allows capacitive LTC1152s to be connected together as a MUX, with their loading of up to 1µF; 0.1µF between pins 5 and 6 allows the outputs tied in parallel and the active channel selected by LTC1152 to drive infinite capacitive load (Figure 3). using the shutdown pins. Deselected (shutdown) chan- nels will go to high impedance at the outputs, preventing 1 8 them from fighting with the active channel. This works 2 7 best when the individual LTC1152s are connected in V+ 3 LTC1152 6 noninverting feedback configurations to prevent the feed- OUTPUT 4 5 back resistors from passing signals through deselected V – 1N4148* channels. See the Typical Applications section for a circuit C 1N4148* C example. *OPTIONAL DIODES TO PREVENT LATCH-UP WITH C 1152 F03 C > 1µF
Zero-Drift Operation Figure 3. Output Compensation Connection
The LTC1152 is a zero-drift op amp. Like other LTC zero- drift op amps, it features virtually error-free DC perfor- mance, very little drift over time and temperature, and very Large compensation capacitors can also be used to limit low noise at low frequencies. The internal nulling clock the bandwidth of the LTC1152. With 0.1µF from pin 5 to runs at about 2.3kHz (the charge pump frequency of pin 6, the LTC1152’s gain-bandwidth product is reduced 4.7MHz divided by 2048) and is synchronized to the from 700kHz to around 200Hz. Note that compensation internal charge pump to prevent beat frequencies from capacitors greater than 1µF can cause latch-up under appearing at the output. The self-nulling circuit constantly severe output fault conditions; this can be prevented by corrects the input offset voltage, keeping it typically below clamping pin 5 to each supply with standard signal diodes, ±1µV over the entire input common-mode range. This has as shown in Figure 3. the added benefit of providing exceptional CMRR and PSRR at low frequencies––far better than competing rail-
Shutdown
to-rail op amps. The LTC1152 includes a shutdown pin (pin 1). When this Because it uses a sampling front end, the LTC1152 will pin is at V +, the LTC1152 operates normally. An internal exhibit aliasing behavior and clock noise at frequencies 1µA pull-up keeps the pin high if it is left floating. When pin near the internal 2.3kHz sampling frequency. The LTC1152 1 is pulled low, the part enters shutdown mode; supply includes an internal anti-aliasing circuit to keep these error current drops to 1µA, all internal clocking stops and the terms to a minimum. As a rule, alias frequencies will be output enters a high impedance state. During shutdown down by (80dB – A the voltage at the CP pin (pin 8) will drop to 0.5V below V +. CLG) in most standard amplifier con- figurations, where A When pin 1 is brought high again, about 10µs will elapse CLG is the closed-loop gain of the LTC1152 circuit. Clock noise is also dependent on closed- before the charge pump regains full voltage. During this loop gain; it will generally consist of spikes of about 100µV time the LTC1152 will operate normally, but the input CMR in amplitude, input referred. In general, these error terms may not include V+. Pin 1 is compatible with CMOS logic are too small to affect most applications. For a more running from the same supply as the LTC1152. Addition- detailed explanation of zero-drift amplifier behavior, see ally, the input trip levels allow ground referenced CMOS the LTC1051/LTC1053 data sheet. logic signals to interface directly to pin 1 when the LTC1152 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7