Datasheet LTC6078, LTC6079 (Analog Devices) - 9

LTC6078/LTC6079
U U W U APPLICATIO S I FOR ATIO Preserving Input Precision Capacitive Load
Preserving input accuracy of the LTC6078/LTC6079 re- LTC6078/LTC6079 can drive capactive load up to 200pF in quires that the application circuit and PC board layout do unity gain. The capacitive load driving capability increases not introduce errors comparable or greater than the 10µV as the amplifi er is used in higher gain confi gurations. A typical offset of the amplifi ers. Temperature differentials small series resistance between the ouput and the load across the input connections can generate thermocouple further increases the amount of capacitance the amplifi er voltages of 10’s of microvolts so the connections to the can drive. input leads should be short, close together and away from heat dissipating components. Air current across the board ⎯
S
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H
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D
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N Pins
can also generate temperature differentials. Pins 5 and 6 are used for power shutdown on the LTC6078 The extremely low input bias currents (0.2pA typical) al- in the DD package. If they are fl oating, internal current low high accuracy to be maintained with high impedance sources pull Pins 5 and 6 to V+ and the amplifi ers operate sources and feedback resistors. Leakage currents on the normally. In shutdown, the amplifi er output is high imped- PC board can be higher than the input bias current. For ance, and each amplifi er draws less than 2µA current. example, 10GΩ of leakage between a 5V supply lead and When the chip is turned on, the supply current per amplifi er an input lead will generate 500pA! Surround the input is about 35µA larger than its normal values for 50µs. leads with a guard ring driven to the same potential as the input common mode to avoid excessive leakage in high
Rail-to-Rail Input
impedance applications. The input stage of LTC6078/LTC6079 combines both PMOS
Input Clamps
and NMOS differential pairs, extending its input common mode voltage range to both positive and negative supply Large differential voltages across the inputs over very voltages. At high input common mode range, the NMOS long time periods can impact the precisely trimmed input pair is on. At low common mode range, the PMOS pair is offset voltage of the LTC6078/LTC6079. As an example, on. The transition happens when the common voltage is a 2V differential voltage between the inputs over a period between 1.3V and 0.9V below the positive supply. of 100 hours can shift the input offset voltage by tens of microvolts. If the amplifi er is to be subjected to large
Thermal Hysteresis
differential input voltages, adding back-to-back diodes Figure 2 shows the input offset hysteresis of LTC6078MS8 between the two inputs will minimize this shift and retain for 3 thermal cycles from –45°C to 90°C. The typical offset the DC precision. If necessary, current-limiting series shift after the 3 cycles is only 1µV. resistors can be added in front of the diodes, as shown in Figure 1. These diodes are not necessary for normal 50 VS = 3V closed loop applications. 45 VCM = 0.5V 1ST CYCLE 40 2ND CYCLE 3RD CYCLE 500Ω 35 + 30 25 500Ω – 20 60789 F01 15 NUMBER OF AMPLIFIERS
Figure 1. Op Amp with Input Voltage Clamp
10 5 0–5 –4 –3 –2 –1 0 1 2 3 4 5 6 VOS CHANGE FROM INITIAL VALUE 60789 F02
Figure 2. VOS Thermal Hysteresis of LTC6078MS8
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