Datasheet ADE7754 (Analog Devices) - 10

ADE7754
Figure 6 shows how the gain settings in PGA 1 (current channel) spreads the quantization noise (noise due to sampling) over a and PGA 2 (voltage channel) are selected by various bits in the wider bandwidth. With the noise spread more thinly over a gain register. The no-load threshold and sum of the absolute wider bandwidth, the quantization noise in the band of interest value can also be selected in the gain register. See Table X. is lowered. See Figure 8. Oversampling alone is not an efficient enough method to
GAIN REGISTER* CURRENT AND VOLTAGE CHANNEL PGA CONTROL
improve the signal to noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required to increase
7 6 5 4 3 2 1 0
the SNR by only 6 dB (1 bit). To keep the oversampling ratio at
0 0 0 0 0 0 0 0 ADDR: 18h
a reasonable level, the quantization noise can be shaped so that most of the noise lies at the higher frequencies. In the Σ-∆
RESERVED = 0 RESERVED = 0 ABS
modulator, the noise is shaped by the integrator, which has a high-pass type of response for the quantization noise. The result
PGA 2 GAIN SELECT PGA 1 GAIN SELECT 00 = 1 NO LOAD 00 = 1
is that most of the noise is at the higher frequencies, where it
01 = 2 01 = 2
can be removed by the digital low-pass filter. This noise shaping
10 = 4 10 = 4
is shown in Figure 8.
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS
Figure 6. Analog Gain Register
ANTIALIAS FILTER (RC) DIGITAL FILTER SAMPLING SHAPED FREQUENCY ANALOG-TO-DIGITAL CONVERSION SIGNAL NOISE
The ADE7754 carries out analog-to-digital conversion using second order Σ-∆ ADCs. The block diagram in Figure 7 shows a first order (for simplicity) Σ-∆ ADC. The converter is made up of
NOISE
two parts, the Σ-∆ modulator and the digital low-pass filter.
0 2 417 833 MCLK/12 FREQUENCY (kHz) ANALOG INTEGRATOR LOW-PASS FILTER LATCHED SIGNAL COMPARATOR HIGH RESOLUTION + OUTPUT FROM DIGITAL LPF R C – VREF 1 24 DIGITAL NOISE LOW-PASS FILTER ..10100101.. 1-BIT DAC 0 2 417 833 FREQUENCY (kHz)
Figure 7. First Order (-) ADC Figure 8. Noise Reduction Due to Oversampling A Σ-∆ modulator converts the input signal into a continuous and Noise Shaping in the Analog Modulator serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7754, the sampling clock is equal to CLKIN/12.
Antialias Filter
The 1-bit DAC in the feedback loop is driven by the serial data Figure 7 shows an analog low-pass filter (RC) on the input to stream. The DAC output is subtracted from the input signal. the modulator. This filter is used to prevent aliasing, an artifact If the loop gain is high enough, the average value of the DAC of all sampled systems. Frequency components in the input output (and therefore the bit stream) will approach that of the signal to the ADC that are higher than half the sampling rate of input signal level. For any given input value in a single sampling the ADC appear in the sampled signal at a frequency below half interval, the data from the 1-bit ADC is virtually meaningless. Only the sampling rate. Figure 9 illustrates the effect; frequency com- when a large number of samples are averaged will a meaningful ponents (arrows shown in black) above half the sampling result be obtained. This averaging is carried out in the second part frequency (also known as the Nyquist frequency), i.e., 417 kHz, of the ADC, the digital low-pass filter. Averaging a large number of get imaged or folded back down below 417 kHz (arrows shown bits from the modulator, the low-pass filter can produce 24-bit in gray). This happens with all ADCs, regardless of the archi- data-words that are proportional to the input signal level. tecture. In the example shown, only frequencies near the sampling frequency, i.e., 833 kHz, will move into the band of interest for The Σ-∆ converter uses two techniques to achieve high resolu- metering, i.e., 40 Hz to 2 kHz. This allows use of a very simple tion from what is essentially a 1-bit conversion technique. The LPF (low-pass filter) to attenuate these high frequencies (near first is oversampling; the signal is sampled at a rate (frequency) 900 kHz) and thus prevent distortion in the band of interest. A many times higher than the bandwidth of interest. For example, simple RC filter (single pole) with a corner frequency of 10 kHz the sampling rate in the ADE7754 is CLKIN/12 (833 kHz), produces an attenuation of approximately 40 dBs at 833 kHz. and the band of interest is 40 Hz to 2 kHz. Oversampling See Figure 9. This is sufficient to eliminate the effects of aliasing. –10– REV. 0 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics TERMINOLOGY Measurement Error Phase Error Between Channels Power Supply Rejection ADC Offset Error Gain Error Gain Error Match POWER SUPPLY MONITOR ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialias Filter CURRENT CHANNEL ADC Current Channel ADC Gain Adjust Current Channel Sampling VOLTAGE CHANNEL ADC ZERO-CROSSING DETECTION Zero-Crossing Timeout PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG Level Set PEAK DETECTION Peak Level Set TEMPERATURE MEASUREMENT PHASE COMPENSATION ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Gain Adjust Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Gain Adjust Voltage RMS Offset Compensation ACTIVE POWER CALCULATION Power Offset Calibration Reverse Power Information TOTAL ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Times Under Steady Load Energy to Frequency Conversion No Load Threshold Mode Selection of the Sum of the Three Active Energies LINE ENERGY ACCUMULATION REACTIVE POWER CALCULATION TOTAL REACTIVE POWER CALCULATION Reactive Energy Accumulation Selection APPARENT POWER CALCULATION Apparent Power Offset Calibration TOTAL APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Integration Times under Steady Load LINE APPARENT ENERGY ACCUMULATION ENERGIES SCALING CHECK SUM REGISTER SERIAL INTERFACE Serial Write Operation Serial Read Operation INTERRUPTS Using Interrupts with an MCU Interrupt Timing ACCESSING THE ADE7754 ON-CHIP REGISTERS Communications Register Operational Mode Register (0Ah) Gain Register (18h) CFNUM Register (25h) Measurement Mode Register (0Bh) Waveform Mode Register (0Ch) Watt Mode Register (0Dh) VA Mode Register (0Eh) Interrupt Enable Register (0Fh) Interrupt Status Register (10h)/Reset Interrupt Status Register (11h) OUTLINE DIMENSIONS