Datasheet ADE7753 (Analog Devices) - 10

link to page 18 link to page 19 link to page 21 link to page 49 link to page 49 link to page 49 link to page 49
ADE7753 Pin No. Mnemonic Description
12 ZX Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section. 13 SAG This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section. 14 IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the ADE7753 Interrupts section. 15 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements. 16 CLKOUT A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. 17 CS Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share the serial bus with several other devices—see the ADE7753 Serial Interface section. 18 SCLK Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator output. 19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see the ADE7753 Serial Interface section. 20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the ADE7753 Serial Interface section. 1 It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 kΩ pull-up resistor. Pull-down resistors are not recommended because under some conditions, they may interact with internal circuitry. Rev. C | Page 10 of 60 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION TERMINOLOGY PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUTS di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR ZERO-CROSSING DETECTION Zero-Crossing Timeout PERIOD MEASUREMENT POWER SUPPLY MONITOR LINE VOLTAGE SAG DETECTION Sag Level Set PEAK DETECTION Peak Level Set Peak Level Record ADE7753 INTERRUPTS Using the ADE7753 Interrupts with an MCU Interrupt Timing TEMPERATURE MEASUREMENT ADE7753 ANALOG-TO-DIGITAL CONVERSION Antialias Filter ADC Transfer Function ADE7753 Reference Circuit CHANNEL 1 ADC Channel 1 Sampling Channel 1 RMS Calculation Channel 1 RMS Offset Compensation CHANNEL 2 ADC Channel 2 Sampling Channel 2 RMS Calculation Channel 2 RMS Offset Compensation PHASE COMPENSATION ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Time under Steady Load POWER OFFSET CALIBRATION ENERGY-TO-FREQUENCY CONVERSION LINE CYCLE ENERGY ACCUMULATION MODE POSITIVE-ONLY ACCUMULATION MODE NO-LOAD THRESHOLD REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION APPARENT POWER CALCULATION Apparent Power Offset Calibration APPARENT ENERGY CALCULATION Integration Times under Steady Load LINE APPARENT ENERGY ACCUMULATION ENERGIES SCALING CALIBRATING AN ENERGY METER BASED ON THE ADE7753 Watt Gain Calibrating Watt Gain Using a Reference Meter Example Calibrating Watt Gain Using an Accurate Source Example Watt Offset Calibrating Watt Offset Using a Reference Meter Example Calibrating Watt Offset with an Accurate Source Example Phase Calibration Calibrating Phase Using a Reference Meter Example Calibrating Phase with an Accurate Source Example VRMS and IRMS Calibration Apparent Energy Reactive Energy CLKIN FREQUENCY SUSPENDING ADE7753 FUNCTIONALITY CHECKSUM REGISTER ADE7753 SERIAL INTERFACE ADE7753 Serial Write Operation ADE7753 Serial Read Operation ADE7753 REGISTERS ADE7753 REGISTER DESCRIPTIONS COMMUNICATIONS REGISTER MODE REGISTER (0x09) INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A) CH1OS REGISTER (0x0D) OUTLINE DIMENSIONS ORDERING GUIDE