Datasheet ADE7880 (Analog Devices) - 6

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ADE7880 Data Sheet Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
RMS MEASUREMENTS (PSM0 Mode) I RMS and V RMS Measurement 3.3 kHz Bandwidth (−3 dB) I RMS and V RMS Measurement Error 0.1 % Over a dynamic range of 1000 to 1, PGA = 1 MEAN ABSOLUTE VALUE (MAV) MEASUREMENT (PSM1 Mode) I MAV Measurement Bandwidth 260 Hz I MAV Measurement Error 0.5 % Over a dynamic range of 100 to 1, PGA = 1, 2, 4, 8 HARMONIC MEASUREMENTS Bandwidth (−3 dB) 3.3 kHz No attenuation Pass Band 2.8 kHz Fundamental Line Frequency, fL 45 66 Hz Voltage signal must have amplitudes greater than 100 mV peak at ADC stage. Set the SELFREQ bit of COMPMODE register based on the frequency. See the Managing Change in Fundamental Line Frequency section for details. Maximum Number of Harmonics3 2800    fL  Absolute Maximum Number of 63 Harmonics Harmonic RMS Measurement Error 1 % Instantaneous reading accuracy over a dynamic range of 1000 to 1 for harmonics of frequencies within the pass band; after the initial 750 ms settling time; PGA = 1 Accuracy over a dynamic range of 2000:1 for harmonics of frequencies within the pass band; average of 10 readings at 128 ms update rate, after the initial 750 ms setting time; PGA = 1 Harmonic Active/Reactive Power 1 % Instantaneous reading accuracy over a Measurement Error dynamic range of 1000 to 1 for harmonics of frequencies within the pass band; after the initial 750 ms settling time; PGA = 1 Accuracy over a dynamic range of 2000:1 for harmonics of frequencies within the pass band; average of 5 readings at 128 ms update rate, after the initial 750 ms setting time; PGA = 1 ANALOG INPUTS Maximum Signal Levels ±500 mV peak PGA = 1, differential or single-ended inputs between the fol owing pins: IAP and IAN, IBP and IBN, ICP and ICN, INP and INN; single-ended inputs between the fol owing pins: VAP and VN, VBP and VN, VCP and VN Input Impedance (DC) IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, 490 kΩ and VCP Pins VN Pin 170 kΩ ADC Offset −35 mV PGA = 1, uncalibrated error, see the Terminology section. Scales inversely proportional to the other PGA gains Gain Error ±4 % External 1.2 V reference Rev. C | Page 6 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0—NORMAL POWER MODE (ALL PARTS) PSM1—REDUCED POWER MODE PSM2—LOW POWER MODE PSM3—SLEEP MODE (ALL PARTS) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET FUNCTIONALITY THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING PHASE VOLTAGE DATA PATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation Managing Change in Fundamental Line Frequency Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Active Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode FUNDAMENTAL REACTIVE POWER CALCULATION Fundamental Reactive Power Gain Calibration Fundamental Reactive Power Offset Calibration Sign of Fundamental Reactive Power Calculation Fundamental Reactive Energy Calculation Integration Time Under Steady Load Fundamental Reactive Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Apparent Energy Accumulation Modes Line Cycle Apparent Energy Accumulation Mode POWER FACTOR CALCULATION HARMONICS CALCULATIONS Harmonics Calcuations Theory Configuring the Harmonic Calculations Harmonic Calculations When a Phase is Monitored Harmonic Calculations When the Neutral is Monitored Configuring Harmonic Calculations Update Rate Recommended Approach to Managing Harmonic Calculations WAVEFORM SAMPLING MODE ENERGY-TO-FREQUENCY CONVERSION Synchronizing Energy Registers with CFx Outputs Energy Registers and CF Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Data Path NO LOAD CONDITION No Load Detection Based On Total Active Power and Apparent Power No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU SERIAL INTERFACES Serial Interface Choice Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Read Operation of Harmonic Calculations Registers SPI-Compatible Interface SPI Read Operation SPI Read Operation of Harmonic Calculations Registers SPI Write Operation HSDC Interface ADE7880 QUICK SETUP AS ENERGY METER LAYOUT GUIDELINES CRYSTAL CIRCUIT ADE7880 EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7880 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADE7880 FUNCTIONALITY ISSUES REGISTERS LIST OUTLINE DIMENSIONS ORDERING GUIDE