Datasheet ADE7854A, ADE7858A, ADE7868A, ADE7878A (Analog Devices) - 8

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ADE7854A/ADE7858A/ADE7868A/ADE7878A Data Sheet Parameter1, 2, 3 Min Typ Max Unit Test Conditions/Comments
ANALOG INPUTS Maximum Signal Levels ±500 mV peak PGA = 1, differential or single-ended inputs between the fol owing pins: IAP and IAN, IBP and IBN, ICP and ICN, INP and INN; single- ended inputs between the following pins: VAP and VN, VBP and VN, VCP and VN Input Impedance (DC) IAP, IAN, IBP, IBN, ICP, ICN, INP, INN, VAP, 400 kΩ VBP, and VCP Pins VN Pin 130 kΩ ADC Offset −34 mV PGA = 1; see the Terminology section Gain Error ±4 % External 1.2 V reference WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Waveform Sampling Mode section Signal-to-Noise Ratio, SNR 74 dB PGA = 1, fundamental frequency = 45 Hz to 65 Hz; see the Terminology section Signal-to-Noise-and-Distortion (SINAD) 74 dB PGA = 1, fundamental frequency = 45 Hz to Ratio 65 Hz; see the Terminology section Bandwidth (−3 dB) 2 kHz TIME INTERVAL BETWEEN PHASES Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle 50 % CF1, CF2, or CF3 frequency > 6.25 Hz, CFDEN is even and > 1 (1 + 1/CFDEN) CF1, CF2, or CF3 frequency > 6.25 Hz, CFDEN × 50% is odd and > 1 Active Low Pulse Width 80 ms CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % CF1, CF2, or CF3 frequency = 1 Hz, nominal phase currents larger than 10% of full scale REFERENCE INPUT REFIN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE, PSM0 AND PSM1 MODES Nominal 1.2 V at the REFIN/OUT pin at TA = 25°C Temperature Coefficient −32 ±5 +32 ppm/°C Drift across the entire temperature range of −40°C to +85°C is calculated with reference to 25°C; see the Reference Circuit section CLKIN CLKIN = 16.384 MHz; see the Crystal Circuit section Input Clock Frequency 16.22 16.384 16.55 MHz LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS /HSA, RESET, PM0, AND PM1 Input High Voltage, VINH 2.0 V VDD = 3.3 V ± 10% Input Low Voltage, VINL 0.8 V VDD = 3.3 V ± 10% Input Current, IIN −8.7 µA Input = 0 V, VDD = 3.3 V 3 µA Input = VDD = 3.3 V Input Capacitance, CIN 10 pF LOGIC OUTPUTS, IRQ0, IRQ1, MISO/HSD Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 10% ISOURCE 800 µA Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10% ISINK 2 mA Rev. C | Page 8 of 96 Document Outline FEATURES GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS TIMING CHARACTERISTICS I2C Interface Timing SPI Interface Timing HSDC Interface Timing Load Circuit for Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0 NORMAL POWER MODE (ALL DEVICES) PSM1 REDUCED POWER MODE (ADE7868A AND ADE7878A ONLY) PSM2 LOW POWER MODE (ADE7868A AND ADE7878A ONLY) PSM2 Interrupt Mode (Default) Setting the Measurement Period Setting the Threshold PSM2 IRQ1/ Only Mode PSM3 SLEEP MODE (ALL DEVICES) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel High-Pass Filter Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING THE PHASE VOLTAGE DATAPATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Delays Between Voltages and Currents Delays Between Phase Voltages Delays Between Phase Currents Power Factor Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch—ADE7868A and ADE7878A PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Low Ripple Current RMS Current RMS Offset Compensation Current Mean Absolute Value Calculation—ADE7868A and ADE7878A Only Current MAV Gain and Offset Compensation Voltage RMS Calculation Low Ripple Voltage RMS Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation—ADE7878A Only Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION—ADE7858A, ADE7868A, ADE7878A ONLY Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Line Cycle Apparent Energy Accumulation Mode WAVEFORM SAMPLING MODE ENERGY TO FREQUENCY CONVERSION Synchronizing Energy Registers with the CFx Outputs CFx Outputs for Various Accumulation Modes Sign of Sum-of-Phase Powers in the CFx Datapath NO LOAD CONDITION No Load Detection Based on Total Active and Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers—ADE7878A Only No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU APPLICATIONS INFORMATION QUICK SETUP OF DEVICES AS ENERGY METERS CRYSTAL CIRCUIT LAYOUT GUIDELINES ADE7878A EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7854A/ADE7858A/ADE7868A/ADE7878A FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SERIAL INTERFACES SERIAL INTERFACE SELECTION COMMUNICATION VERIFICATION I2C-COMPATIBLE INTERFACE I2C Write Operation I2C Read Operation SPI-COMPATIBLE INTERFACE SPI Write Operation SPI Read Operation SPI Burst Read Operation HSDC INTERFACE REGISTER LIST OUTLINE DIMENSIONS ORDERING GUIDE