Datasheet ADE7978, ADE7933, ADE7932, ADE7923 (Analog Devices) - 6

ADE7978/ADE7933/ADE7932/ADE7923 Data Sheet FUNCTIONAL BLOCK DIAGRAMS RESET VDD GND LDO DGND 12 21 20 22 23 ADE7978 POR LDO AV2RMSOS HPFEN BIT AV2GAIN 27 X2 AV2RMS HPF LPF XTALIN 25 ATEMP AIRMSOS XTALOUT 24 SELECTION BIT VB/TEMP SENSOR ATGAIN APGAIN ATEMP0 X2 AIRMS 211 LPF VT_B 1 TEMPCO ATEMPOS DATA_B 2 1 X2 AVRMS LPF AIGAIN HPFEN BIT CF1DEN RESET_EN 3 AVRMSOS DFC APGAIN AWATTOS : 13 CF1 HPF CLKOUT 4 CF2DEN DIGITAL APHCAL HPFEN BIT BLOCK LPF SYNC 5 PHASE A, : 14 CF2 PHASE B, DFC PHASE C DATA CF3DEN HPF VT_C 6 APGAIN AVAROS AV1GAIN COMPUTATIONAL DFC : 15 CF3/HSCLK BLOCK FOR TOTAL DATA_C 7 REACTIVE POWER ACTIVE/REACTIVE/APPARENT APGAIN AFWATTOS 26 ZX/DREADY TOTAL ENERGIES AND VT_N 8 VOLTAGE/CURRENT RMS 10 IRQ0 CALCULATION FOR PHASE B (SEE PHASE A FOR DETAILED 11 IRQ1 DATAPATH) COMPUTATIONAL DATA_N 9 BLOCK FOR APGAIN AFVAROS FUNDAMENTAL 17 SCLK/SCL ACTIVE AND ACTIVE/REACTIVE/APPARENT REACTIVE POWER TOTAL ENERGIES AND SPI OR 19 MOSI/SDA VT_A 27 VOLTAGE/CURRENT RMS I2C AND CALCULATION FOR PHASE C TEMPCO DIGITAL SIGNAL HSDC 18 MISO/HSD (SEE PHASE A FOR DETAILED NTEMP DATAPATH) PROCESSOR DATA_A 28 16 SS/HSA HPFEN NTEMP0 BIT NIGAIN NIRMSOS 1 X2 NIRMS HPF LPF
002 11116- Figure 2. ADE7978 Functional Block Diagram Rev. D | Page 6 of 125 Document Outline Features Applications Typical Application Circuit Revision History General Description Functional Block Diagrams Specifications System Specifications, ADE7978 and ADE7933/ADE7932/ADE7923 ADE7978 Specifications I2C Interface Timing Parameters SPI Interface Timing Parameters HSDC Interface Timing Parameters ADE7933/ADE7932 Specifications Regulatory Approvals Insulation and Safety Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ADE7923 Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Total Energy Linearity over Supply and Temperature Fundamental Energy and RMS Linearity with Fifth Harmonic over Supply and Temperature Total Energy Error over Frequency RMS Linearity over Temperature and RMS Error over Frequency Energy Linearity Repeatability Cumulative Histograms of ADC Gain Temperature Coefficients Test Circuit Terminology Theory of Operation ADE7933/ADE7932/ADE7923 Analog Inputs Analog-to-Digital Conversion Oversampling Noise Shaping Antialiasing Filter ADC Transfer Function Untitled Current Channel ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling Voltage Channel ADCs Second Voltage Channel and Temperature Measurement Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling Changing the Phase Voltage Datapath Reference Circuits Phase Compensation Digital Signal Processor Power Quality Measurements Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Detection Level Setting Peak Detection Overvoltage and Overcurrent Detection Overvoltage Detection Overcurrent Detection Overvoltage and Overcurrent Level Setting Neutral Current Mismatch Root Mean Square Measurement Current RMS Calculation Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Offset Compensation Voltage RMS in Delta Configurations Active Power Calculation Total Active Power Calculation Fundamental Active Power Calculation Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Active Energy Accumulation Mode Reactive Power Calculation Total Reactive Power Calculation Fundamental Reactive Power Calculation Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Reactive Energy Accumulation Mode Apparent Power Calculation Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Apparent Energy Accumulation Mode Power Factor Calculation and Total Harmonic Distortion Calculation Power Factor Calculation Total Harmonic Distortion Calculation Waveform Sampling Mode Energy-to-Frequency Conversion TERMSELx[2:0] Bits CFxSEL[2:0] Bits Energy-to-Frequency Conversion Process Synchronizing Energy Registers with the CFx Outputs Energy Registers and CFx Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Datapath No Load Condition No Load Detection Based on Total Active and Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power Interrupts Using the Interrupts with an MCU Power Management DC-to-DC Converter Magnetic Field Immunity Power-Up Procedure Initializing the Chipset Hardware Reset ADE7978/ADE7933/ADE7932 and ADE7923 Chipset Software Reset ADE7933/ADE7932 and ADE7923 Software Reset Low Power Mode Applications Information Differences Between the ADE7923 and the ADE7933/ADE7932 ADE7978, ADE7933/ADE7932 and ADE7923 in Polyphase Energy Meters ADE7978 Quick Setup as an Energy Meter Bit Stream Communication Between the ADE7978 and the ADE7933/ADE7932 and ADE7923 ADE7978, ADE7933/ADE7932, and ADE7923 Clocks Insulation Lifetime Layout Guidelines ADE7978 and ADE7933/ADE7932 Evaluation Board ADE7978 Die Version Serial Interfaces Serial Interface Selection Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Burst Read Operation SPI-Compatible Interface SPI Write Operation SPI Read Operation SPI Burst Read Operation HSDC Interface Checksum Register Register List Outline Dimensions Ordering Guide