Datasheet ADE9153A (Analog Devices) - 4

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ADE9153A Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
ADC PGA Gain Settings (xI_PGAGAIN) Current Channel A (Phase Shunt) 16, 24, V/V PGA gain setting is referred to as gain 32, 38.4 Current Channel B (Neutral CT) 1, 2, 4 V/V PGA gain setting is referred to as gain Pseudo Differential Input Voltage Range (IAP − IAN) −1/gain +1/gain V 44.19 mV rms on Current Channel A, AI_PGAGAIN = 16× (VAP − VAN) −0.5 +0.5 V 353.6 mV rms on voltage channel Differential Input Voltage Range (IBP − IBN) −1/gain +1/gain V 707 mV rms on Current Channel B Maximum Operating Voltage on the Analog Input Pins VAP 0 1.35 V Voltage on the pin with respect to ground IAP, IAN −0.1125 +0.1125 V Voltage on the IAx pin with respect to ground IBP, IBN 0.35 1.45 V Voltage on the IBx pin with respect to ground; internal common-mode voltage at IBx pin = 0.9 V SNR Current Channel A AI_PGAGAIN = 16× 90 dB VIN is a full-scale signal AI_PGAGAIN = 38.4× 88 dB VIN is a full-scale signal Current Channel B BI_PGAGAIN = 1x 90 dB VIN is a full-scale signal BI_PGAGAIN = 4x 78 dB VIN is a full-scale signal Voltage Channel 87 dB VIN is a full-scale signal ADC Output Pass Band (0.1 dB) 0.672 kHz ADC Output Bandwidth (−3 dB) 1.6 kHz Crosstalk −120 dB At 50 Hz or 60 Hz; see the Terminology section AC Power Supply Rejection Ratio At 50 Hz; see the Terminology section (AC PSRR) Current Channel A −115 dB Current Channel B −100 dB Voltage Channel −100 dB AC Common-Mode Rejection Ratio −120 dB At 50 Hz (AC CMRR) ADC Gain Error Percentage of error from the ideal value; see the Terminology section Current Channel A ±0.2 ±1.5 % Current Channel B −2.0 ±3.5 % Voltage Channel −0.8 ±3.0 % ADC Offset Current Channel A See the Terminology section AI_PGAGAIN = 16× +0.04 ±0.1 mV AI_PGAGAIN = 38.4× −0.02 ±0.05 mV Current Channel B −0.26 ±0.37 mV Voltage Channel +0.35 ±0.75 mV ADC Offset Drift ±0.5 ±5 μV/°C See the Terminology section Rev. 0 | Page 4 of 50 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATIONS CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AUTOCALIBRATION SPI TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY SIGNAL-TO-NOISE RATIO (SNR) PERFORMANCE OVER DYNAMIC RANGE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION mSURE AUTOCALIBRATION FEATURE mSure System Warning Interrupts MEASUREMENTS Current Channel Current Channel Gain, xIGAIN High-Pass Filter Digital Integrator Phase Compensation Voltage Channel RMS and Power Measurements Total RMS Total Active Power Fundamental Reactive Power Total Apparent Power Energy Accumulation, Power Accumulation, and No Load Detection Features Energy Accumulation Energy Accumulation Modes Reset Energy Register on Read Power Accumulation No Load Detection Feature Digital to Frequency Conversion—CFx Output Calibration Frequency (CF) Energy Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF1/ZX/DREADY Zero-Crossing Timeout Line Period Calculation Angle Measurement One Cycle RMS Measurement Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Temperature APPLICATIONS INFORMATION INTERRUPTS/EVENTS PIN INTERRUPTS SERVICING INTERRUPTS CF2/ZX/DREADY EVENT PIN ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW UART INTERFACE COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER INFORMATION REGISTER SUMMARY REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE