Datasheet LTC4100 (Analog Devices) - 10

LTC4100
TesT circuiT
LTC4100 1.19V + – EA VBAT − V – V VDAC •100 + TOL = VVDAC V FOR V DAC VDAC = 17.57V(0x44A0) 21 22 18 19 CSP BAT VSET ITH DCIN = 21V + LT1055 CLN = CLP = 20V – 0.6V 4100 TC01
operaTion Overview (Refer to Block Diagram)
BATTERY_PRESENT, ALARM_INHIBITED, or VDD power- The LTC4100 is composed of a battery charger section, a fail. The host may query the charger, via the SMBus, to charger controller, a 10-bit DAC to control charger current, obtain ChargerStatus() information. SMBALERT will be an 11-bit DAC to control charger voltage, a SafetySignal de-asserted upon a successful read of ChargerStatus() decoder, limit decoder and an SMBus controller block. If or a successful Alert Response Address (ARA) request. no battery is present, the SafetySignal decoder indicates a
Battery Charger Controller
RES_OR condition and charging is disabled by the charger controller (CHGEN = Low). Charging will also be disabled if The LTC4100 charger controller uses a constant off-time, DCDIV is low, or the SafetySignal is decoded as RES_HOT. current mode step-down architecture. During normal If a battery is inserted and AC power is connected, the operation, the top MOSFET is turned on each cycle when battery will be charged with an 80mA “wake-up” current. the oscillator sets the SR latch and turned off when The wake-up current is discontinued after t the main current comparator I TIMEOUT if the CMP resets the SR latch. SafetySignal is decoded as RES_UR or RES_C0LD, and While the top MOSFET is off, the bottom MOSFET is the battery or host doesn’t transmit charging commands. turned on until either the inductor current trips the current comparator I The SMBus interface and control block receives Charg- REV, or the beginning of the next cycle. The oscillator uses the equation, ingCurrent() and ChargingVoltage() commands via the SMBus. If ChargingCurrent() and ChargingVoltage() (VDCIN − VBAT) command pairs are received within a t t TIMEOUT interval, the OFF = (V ) values are stored in the current and voltage DACs and the DCIN • fOSC charger controller asserts the CHGEN line if the decoded to set the bottom MOSFET on-time. The result is quasi- SafetySignal value will allow charging to commence. Charg- constant frequency operation: the converter frequency ingCurrent() and ChargingVoltage() values are compared remains nearly constant over a wide range of output volt- against limits programmed by the limit decoder block; if ages. This activity is diagrammed in Figure 3. the commands exceed the programmed limits these limits are substituted and overrange flags are set. The peak inductor current, at which ICMP resets the SR latch, is controlled by the voltage on ITH. ITH is in turn The charger controller will assert SMBALERT whenever controlled by several loops, depending upon the situation a status change is detected, namely: AC_PRESENT, at hand. The average current control loop converts the 4100fc 10 For more information www.linear.com/LTC4100