Datasheet LTC4006 (Analog Devices) - 8

LTC4006
U OPERATIO Overview
ACP/SHDN pin. It controls the gate of the input FET to keep a low forward voltage drop when charging and also The LTC4006 is a synchronous current mode PWM step- prevents reverse current flow through the input FET. down (buck) switcher battery charger controller. The charge current is programmed by the sense resistor (RSENSE) If the input voltage is less than VCLN, it must go at least between the CSP and BAT pins. The final float voltage is 170mV higher than VCLN to activate the charger. When this internally programmed to 8.4V (LTC4006-6), 12.6V occurs the ACP/SHDN pin is released and pulled up with (LTC4006-2) or 16.8V (LTC4006-4) with better than ±0.8% an internal load to indicate that the adapter is present. The accuracy. Charging begins when the potential at the DCIN gate of the input FET is driven to a voltage sufficient to keep pin rises above the voltage at CLN (and the UVLO voltage) a low forward voltage drop from drain to source. If the and the ACP/SHDN pin is allowed to go high; the CHG pin voltage between DCIN and CLN drops to less than 25mV, is set low. At the beginning of the charge cycle, if the cell the input FET is turned off slowly. If the voltage between voltage is below 2.5V, the charger will trickle charge the DCIN and CLN is ever less than – 25mV, then the input FET battery with 10% of the maximum programmed current. is turned off in less than 10µs to prevent significant If the cell voltage stays below 2.5V for 25% of the total reverse current from flowing in the input FET. In this charge time, the charge sequence will be terminated im- condition, the ACP/SHDN pin is driven low and the charger mediately and the CHG pin will be set to a high impedance. is disabled. An external thermistor network is sampled at regular
Battery Charger Controller
intervals. If the thermistor value exceeds design limits, charging is suspended. If the thermistor value returns to The LTC4006 charger controller uses a constant off-time, an acceptable value, charging resumes. An external resis- current mode step-down architecture. During normal opera- tor on the R tion, the top MOSFET is turned on each cycle when the T pin sets the total charge time. The timer can be defeated by forcing the CHG pin to a low voltage. oscillator sets the SR latch and turned off when the main current comparator I As the battery approaches the final float voltage, the charge CMP resets the SR latch. While the top MOSFET is off, the bottom MOSFET is turned on until either current will begin to decrease. When the current drops to the inductor current trips the current comparator I 10% of the programmed charge current, an internal C/10 REV or the beginning of the next cycle. The oscillator uses the equation: comparator will indicate this condition by sinking 25µA at the CHG pin. The charge timer is also reset to 25% of the total V V t DCIN BAT = – charge time. If this condition is caused by an input current OFF V • f DCIN OSC limit condition, described below, then the C/10 comparator will be inhibited. When a time-out occurs, charging is termi- to set the bottom MOSFET on time. This activity is dia- nated immediately and the CHG pin changes to a high grammed in Figure 1. impedance. The charger will automatically restart if the cell The peak inductor current, at which ICMP resets the SR latch, voltage is less than 3.9V. To restart the charge cycle manu- is controlled by the voltage on ITH. ITH is in turn controlled by ally, simply remove the input voltage and reapply it, or force several loops, depending upon the situation at hand. The the ACP/SHDN pin low momentarily. When the input voltage average current control loop converts the voltage between is not present, the charger goes into a sleep mode, dropping CSP and BAT to a representative current. Error amp CA2 battery current drain to 15µA. This greatly reduces the current OFF drain on the battery and increases the standby time. The TGATE charger can be inhibited at any time by forcing the ACP/SHDN ON ON pin to a low voltage. BGATE tOFF OFF
Input FET
TRIP POINT SET BY ITH VOLTAGE The input FET circuit performs two functions. It enables INDUCTOR CURRENT the charger if the input voltage is higher than the CLN pin 4006 F01 and provides the logic indicator of AC present on the
Figure 1
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