Datasheet ADP5090 (Analog Devices) - 5

Data Sheet ADP5090 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W PG _S F S GOOD SET RE DI P 16 15 14 13 SETSD 1 12 BACK_UP TERM 2 11 SYS ADP5090 AGND 3 TOP VIEW 10 BAT MINOP 4 9 SW 5 6 7 8 P N ND CB VI G MPPT P
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NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
12263- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SETSD Shutdown Setting. This pin sets the shutdown discharging voltage based on the BAT node voltage level. 2 TERM Termination Charging Voltage. This pin sets the terminal charging voltage based on the BAT node voltage level. 3 AGND Analog Ground. Connect the exposed pad to the analog ground on the board. 4 MINOP Minimum Operating Power. Place a resistor on this pin to set the minimum operation input voltage level. The boost regulator starts switching after the CBP voltage exceeds the MINOP voltage. Connect this pin to AGND to disable MINOP function. 5 MPPT Maximum Power Point Tracking. This pin sets the maximum power point tracking level for different energy harvesters. To disable MPPT, float this pin. 6 CBP Capacitor Bypass. Samples and holds the maximum power point level. Connect a 10 nF capacitor from this pin to AGND. When MPPT is disabled, tie CBP to an external reference that is lower than VIN. 7 VIN Input Supply from Energy Harvester Source. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. 8 PGND Power Ground. 9 SW Switching Node for the Inductive Boost Regulator with a Connection to the External Inductor. Connect a 22 μH inductor between this pin and VIN. 10 BAT Places Rechargeable Battery or Super Capacitor as a Storage for SYS Output Supply. 11 SYS Output Supply to System Load. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. 12 BACK_UP Optional Input Supply from the Backup Primary Battery Cell. 13 PGOOD Output Supply. Maintain a logic high signal when SYS voltage is higher than the SETPG threshold. 14 DIS_SW Control Signal from the MCU or RF Transceiver. Stop the main boost switching by pulling this pin high. Enable the main boost switching by pulling this pin low. 15 REF Provides Bias Voltage for the SETSD, TERM, and SETPG Pins. Connect the high side of the resistor divider networks to this bias voltage. 16 SETPG Sets Power Good Voltage Based on the SYS Node Voltage Level. EPAD Exposed Pad. The exposed pad must be connected to AGND. Rev. C | Page 5 of 21 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION COLD STARTUP (VSYS < VSYS_TH, VIN > VIN_COLD) BOOST REGULATOR (VBAT_TERM > VSYS ≥ VSYS_TH) VIN OPEN CIRCUIT AND MPPT ENERGY STORAGE CHARGE MANAGEMENT BACKUP STORAGE PATH MINOP FUNCTION DISABLING BOOST BATTERY OVERCHARGING PROTECTION BATTERY DISCHARGING PROTECTION POWER GOOD (PGOOD) POWER PATH WORKING FLOW CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ENERGY HARVESTER SELECTION ENERGY STORAGE ELEMENT SELECTION INDUCTOR SELECTION CAPACITOR SELECTION Input Capacitor SYS Capacitor CBP Capacitor LAYOUT AND ASSEMBLY CONSIDERATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE