Datasheet LTC4162-F (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 35V/3.2A Multi-Cell LiFePO4 Step-Down Battery Charger with PowerPath and I2C Telemetry |
| Páginas / Página | 50 / 5 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the full specified
Versión de texto del documento
link to page 47 LTC4162-F
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL
PARAMETER CONDITIONS
MIN TYP MAX UNITS
fOSC Switching Frequency RT = 63.4k l 1.4 1.5 1.6 MHz DMAX Maximum Duty Cycle 99.5 % RSWITCH Primary Switch On-Resistance 90 mΩ RRECT Rectifier Switch On-Resistance 90 mΩ IPEAK Peak Inductor Current Limit Note 3 45mV/RSNSB A
System Controls
VIN_UVLO VIN Charger Enable Rising Threshold 4.2 4.4 4.6 V Input Undervoltage Lockout Hysteresis 0.2 V VIN_DUVLO VIN to BATSENS+ Charger Enable Rising Threshold 100 150 200 mV Differential Undervoltage Lockout Hysteresis 170 mV VIN_OVLO VIN Charger Disable Rising Threshold 37.6 38.6 40 V Overvoltage Lockout Hysteresis 1.4 V VINTVCC_UVLO INTVCC Telemetry Enable Rising Threshold 2.75 2.85 2.95 V Undervoltage Lockout Hysteresis 0.12 V
Telemetry A/D Measurement Subsystem
IBAT Resolution IBAT = (VCSP – VCSN)/RSNSB 1.466 µV /LSB (VCSP – VCSN) Offset Error 0.32mV < VCSP – VCSN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng IIN Resolution IIN = (VCLP – VCLN)/RSNSI 1.466 µV/LSB (VCLP – VCLN) Offset Error 0.32mV < VCLP – VCLN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng VIN Resolution 1.649 mV/LSB Offset Error 3V < VIN < 35V –25 25 mV Span Error –1 1 %rdng VBATSENS+ Resolution 192.4 µV/LSB (Per cell_count) Offset Error 2V < VBATSENS+ < 3.8V –10 10 mV Span Error –1 1 %rdng VOUT Resolution 1.653 mV/LSB Offset Error 3V < VOUT < 35V –25 25 mV Span Error –1 1 %rdng VNTC/VNTCBIAS Resolution 45.833 µV/V/LSB Offset Error 0 < VNTC/VNTCBIAS < 1 –1 1 mV/V Span Error –1 1 %rdng T_die Resolution 0.0215 °C/LSB Offset –264.4 °C
Serial Port, SDA, SCL, SMBALERT
DVCC Logic Reference Level l 1.8 5.5 V IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA ADDRESS I2C Address 0b1101000[R/W] VIHI2C Input High Threshold 70 % DVCC VILI2C Input Low Threshold 30 % DVCC VOLI2C Digital Output Low (SDA/SCL/SMBALERT) ISDA/SCL/SMBALERT = 3mA 400 mV FSCL SCL Clock Frequency 400 kHz Rev 0 For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Typical Application Related Parts
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL
PARAMETER CONDITIONS
MIN TYP MAX UNITS
fOSC Switching Frequency RT = 63.4k l 1.4 1.5 1.6 MHz DMAX Maximum Duty Cycle 99.5 % RSWITCH Primary Switch On-Resistance 90 mΩ RRECT Rectifier Switch On-Resistance 90 mΩ IPEAK Peak Inductor Current Limit Note 3 45mV/RSNSB A
System Controls
VIN_UVLO VIN Charger Enable Rising Threshold 4.2 4.4 4.6 V Input Undervoltage Lockout Hysteresis 0.2 V VIN_DUVLO VIN to BATSENS+ Charger Enable Rising Threshold 100 150 200 mV Differential Undervoltage Lockout Hysteresis 170 mV VIN_OVLO VIN Charger Disable Rising Threshold 37.6 38.6 40 V Overvoltage Lockout Hysteresis 1.4 V VINTVCC_UVLO INTVCC Telemetry Enable Rising Threshold 2.75 2.85 2.95 V Undervoltage Lockout Hysteresis 0.12 V
Telemetry A/D Measurement Subsystem
IBAT Resolution IBAT = (VCSP – VCSN)/RSNSB 1.466 µV /LSB (VCSP – VCSN) Offset Error 0.32mV < VCSP – VCSN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng IIN Resolution IIN = (VCLP – VCLN)/RSNSI 1.466 µV/LSB (VCLP – VCLN) Offset Error 0.32mV < VCLP – VCLN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng VIN Resolution 1.649 mV/LSB Offset Error 3V < VIN < 35V –25 25 mV Span Error –1 1 %rdng VBATSENS+ Resolution 192.4 µV/LSB (Per cell_count) Offset Error 2V < VBATSENS+ < 3.8V –10 10 mV Span Error –1 1 %rdng VOUT Resolution 1.653 mV/LSB Offset Error 3V < VOUT < 35V –25 25 mV Span Error –1 1 %rdng VNTC/VNTCBIAS Resolution 45.833 µV/V/LSB Offset Error 0 < VNTC/VNTCBIAS < 1 –1 1 mV/V Span Error –1 1 %rdng T_die Resolution 0.0215 °C/LSB Offset –264.4 °C
Serial Port, SDA, SCL, SMBALERT
DVCC Logic Reference Level l 1.8 5.5 V IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA ADDRESS I2C Address 0b1101000[R/W] VIHI2C Input High Threshold 70 % DVCC VILI2C Input Low Threshold 30 % DVCC VOLI2C Digital Output Low (SDA/SCL/SMBALERT) ISDA/SCL/SMBALERT = 3mA 400 mV FSCL SCL Clock Frequency 400 kHz Rev 0 For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Typical Application Related Parts