Datasheet LTC4361-1, LTC4361-2 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Overvoltage/Overcurrent Protection Controller |
| Páginas / Página | 16 / 8 — APPLICATIONS INFORMATION. PWRGD Output. Figure 2. PWRGD Behavior |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 628 Kb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION. PWRGD Output. Figure 2. PWRGD Behavior
Línea de modelo para esta hoja de datos
- LTC4361CDC-1#PBF LTC4361CDC-1#TRMPBF LTC4361CDC-1#TRPBF LTC4361CDC-2#PBF LTC4361CDC-2#TRMPBF LTC4361CDC-2#TRPBF LTC4361CTS8-1#PBF LTC4361CTS8-1#TRMPBF LTC4361CTS8-1#TRPBF LTC4361CTS8-2#PBF LTC4361CTS8-2#TRMPBF LTC4361CTS8-2#TRPBF LTC4361HDC-1#PBF LTC4361HDC-1#TRMPBF LTC4361HDC-1#TRPBF LTC4361HDC-2#PBF LTC4361HDC-2#TRMPBF LTC4361HDC-2#TRPBF LTC4361HTS8-1#PBF LTC4361HTS8-1#TRMPBF LTC4361HTS8-1#TRPBF LTC4361HTS8-2#PBF LTC4361HTS8-2#TRMPBF LTC4361HTS8-2#TRPBF LTC4361IDC-1#PBF LTC4361IDC-1#TRMPBF LTC4361IDC-1#TRPBF LTC4361IDC-2#PBF LTC4361IDC-2#TRMPBF LTC4361IDC-2#TRPBF LTC4361ITS8-1#PBF LTC4361ITS8-1#TRMPBF LTC4361ITS8-1#TRPBF LTC4361ITS8-2#PBF LTC4361ITS8-2#TRMPBF LTC4361ITS8-2#TRPBF
Versión de texto del documento
link to page 8 LTC4361-1/LTC4361-2
APPLICATIONS INFORMATION
to apply power again after a 130ms start-up delay.
PWRGD Output
The LTC4361-1 has an internal latch that maintains this PWRGD is an active low output with a MOSFET pull-down off state until it is reset. To reset this latch, cycle IN below to ground and a 500k resistive pull-up to OUT. The PWRGD 2.1V (VIN(UVL)) or ON above 1.5V (VON(TH)) for more than pin pul -down releases during the low current sleep mode 500µs. After reset, the LTC4361-1 goes through the start- (invoked by ON high), UVLO, overvoltage or overcurrent up cycle. and the subsequent 130ms start-up delay. After the start- In applications not requiring the overcurrent protection, up delay, GATE starts its slow ramp-up and control of tie the SENSE pin to the IN pin. To implement an overcur- the PWRGD pull-down passes on to the GATE high com- rent threshold ITRIP , choose RSENSE using the formula: parator. VGATE > VGATE(TH) for more than 65ms asserts the PWRGD pull-down and VGATE < VGATE(TH) releases R ∆VOC SENSE = the pull-down. The PWRGD pull-down is capable of sink- ITRIP ing up to 3mA of current allowing it to drive an optional After choosing the R LED. To interface PWRGD to another I/O rail, connect a SENSE, keep in mind that: resistor from PWRGD to the I/O rail with a resistance ∆V low enough to override the internal 500k pull-up to OUT. I OC(MAX) TRIP(MAX) = R Figure 2 details PWRGD behavior for a LTC4361-2 with SENSE(MIN) 1k pull-up to 5V at PWRGD. ∆V I OC(MIN) TRIP(MIN) = R SENSE(MAX) START-UP RESTART RESTART OC RESTART FROM UVLO OV FROM OV ON FROM ON FROM OC OC THRESHOLD ICABLE VIN(OV) VIN(OV)–∆VOV VIN(UVL) IN OUT VGATE(TH) VGATE(TH) VGATE(TH) VGATE(TH) VGATE(TH) GATE ON PWRGD 130ms 65ms 130ms 65ms 130ms 65ms 130ms 65ms 10µs (NOT TO SCALE) 436112 F02
Figure 2. PWRGD Behavior
Rev C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION
to apply power again after a 130ms start-up delay.
PWRGD Output
The LTC4361-1 has an internal latch that maintains this PWRGD is an active low output with a MOSFET pull-down off state until it is reset. To reset this latch, cycle IN below to ground and a 500k resistive pull-up to OUT. The PWRGD 2.1V (VIN(UVL)) or ON above 1.5V (VON(TH)) for more than pin pul -down releases during the low current sleep mode 500µs. After reset, the LTC4361-1 goes through the start- (invoked by ON high), UVLO, overvoltage or overcurrent up cycle. and the subsequent 130ms start-up delay. After the start- In applications not requiring the overcurrent protection, up delay, GATE starts its slow ramp-up and control of tie the SENSE pin to the IN pin. To implement an overcur- the PWRGD pull-down passes on to the GATE high com- rent threshold ITRIP , choose RSENSE using the formula: parator. VGATE > VGATE(TH) for more than 65ms asserts the PWRGD pull-down and VGATE < VGATE(TH) releases R ∆VOC SENSE = the pull-down. The PWRGD pull-down is capable of sink- ITRIP ing up to 3mA of current allowing it to drive an optional After choosing the R LED. To interface PWRGD to another I/O rail, connect a SENSE, keep in mind that: resistor from PWRGD to the I/O rail with a resistance ∆V low enough to override the internal 500k pull-up to OUT. I OC(MAX) TRIP(MAX) = R Figure 2 details PWRGD behavior for a LTC4361-2 with SENSE(MIN) 1k pull-up to 5V at PWRGD. ∆V I OC(MIN) TRIP(MIN) = R SENSE(MAX) START-UP RESTART RESTART OC RESTART FROM UVLO OV FROM OV ON FROM ON FROM OC OC THRESHOLD ICABLE VIN(OV) VIN(OV)–∆VOV VIN(UVL) IN OUT VGATE(TH) VGATE(TH) VGATE(TH) VGATE(TH) VGATE(TH) GATE ON PWRGD 130ms 65ms 130ms 65ms 130ms 65ms 130ms 65ms 10µs (NOT TO SCALE) 436112 F02
Figure 2. PWRGD Behavior
Rev C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts