Datasheet LTC4361-1, LTC4361-2 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Overvoltage/Overcurrent Protection Controller |
| Páginas / Página | 16 / 6 — BLOCK DIAGRAM. OPERATION |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 628 Kb |
| Idioma del documento | Inglés |
BLOCK DIAGRAM. OPERATION
Línea de modelo para esta hoja de datos
- LTC4361CDC-1#PBF LTC4361CDC-1#TRMPBF LTC4361CDC-1#TRPBF LTC4361CDC-2#PBF LTC4361CDC-2#TRMPBF LTC4361CDC-2#TRPBF LTC4361CTS8-1#PBF LTC4361CTS8-1#TRMPBF LTC4361CTS8-1#TRPBF LTC4361CTS8-2#PBF LTC4361CTS8-2#TRMPBF LTC4361CTS8-2#TRPBF LTC4361HDC-1#PBF LTC4361HDC-1#TRMPBF LTC4361HDC-1#TRPBF LTC4361HDC-2#PBF LTC4361HDC-2#TRMPBF LTC4361HDC-2#TRPBF LTC4361HTS8-1#PBF LTC4361HTS8-1#TRMPBF LTC4361HTS8-1#TRPBF LTC4361HTS8-2#PBF LTC4361HTS8-2#TRMPBF LTC4361HTS8-2#TRPBF LTC4361IDC-1#PBF LTC4361IDC-1#TRMPBF LTC4361IDC-1#TRPBF LTC4361IDC-2#PBF LTC4361IDC-2#TRMPBF LTC4361IDC-2#TRPBF LTC4361ITS8-1#PBF LTC4361ITS8-1#TRMPBF LTC4361ITS8-1#TRPBF LTC4361ITS8-2#PBF LTC4361ITS8-2#TRMPBF LTC4361ITS8-2#TRPBF
Versión de texto del documento
LTC4361-1/LTC4361-2
BLOCK DIAGRAM
GATEP IN SENSE 200k 5.8V CHARGE PUMP 1.8M 10µA GATE ON GATE HIGH 5.8V + COMPARATOR 1V – + OUT 5µA – V OVERCURRENT GATE(TH) COMPARATOR + 50mV + – – CONTROL OVERVOLTAGE 500k COMPARATOR + 5.8V – 5.7V PWRGD GND 436112 BD
OPERATION
Mobile devices like cell phones and MP3/MP4 players have If the voltage at the IN pin exceeds 5.8V (VIN(OV)), highly integrated subsystems fabricated from deep submi- GATE is pulled low quickly to protect the load. The cron CMOS processes. The small form factor is accompa- incoming power supply must remain below 5.7V nied by low absolute maximum voltage ratings. The sensi- (VIN(OV) – ∆VOV) for the duration of the start-up delay to tive electronics are susceptible to damage from transient or restart the GATE ramp-up. DC overvoltage conditions from the power supply. A sense resistor placed between IN and SENSE imple- Failures or faults in the power adaptor can cause an overvolt- ments an overcurrent protection with a 50mV trip age event. So can hot-plugging an AC adaptor into the power threshold and a 10µs glitch filter. After an overcurrent, input of the mobile device (see ADI Application Note 88). the LTC4361-1 latches off while the LTC4361-2 restarts Today’s mobile devices derive their power supply or recharge following a 130ms delay. their internal batteries from multiple alternative inputs like AC The LTC4361 has a CMOS compatible ON input. When wall adaptors, car battery adaptors and USB ports. A user driven low, the part is enabled. When driven high, the may unknowingly plug in the wrong adaptor, damaging the external N-channel MOSFET is turned off and the supply device with a high or even a negative power supply voltage. current of the LTC4361 drops to 1.5µA. The PWRGD pull- The LTC4361 protects low voltage electronics from these down releases during this low current sleep mode, UVLO, overvoltage conditions by controlling a low cost external overvoltage or overcurrent and the subsequent 130ms N-channel MOSFET configured as a pass transistor. At start-up delay. After the start-up delay, GATE starts its power-up (VIN > 2.1V), a start-up delay cycle begins. Any slow ramp-up and ramps higher than VGATE(TH) to trigger overvoltage condition causes the delay cycle to continue a 65ms delay cycle. When that completes, PWRGD pulls until a safe voltage is present. When the delay cycle com- low. The LTC4361 has a GATEP pin that drives an optional pletes, an internal high side switch driver slowly ramps up external P-channel MOSFET to provide protection against the MOSFET gate, powering up the output at a controlled negative voltages at IN. rate and limiting the inrush current to the output capacitor. Rev C 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
BLOCK DIAGRAM
GATEP IN SENSE 200k 5.8V CHARGE PUMP 1.8M 10µA GATE ON GATE HIGH 5.8V + COMPARATOR 1V – + OUT 5µA – V OVERCURRENT GATE(TH) COMPARATOR + 50mV + – – CONTROL OVERVOLTAGE 500k COMPARATOR + 5.8V – 5.7V PWRGD GND 436112 BD
OPERATION
Mobile devices like cell phones and MP3/MP4 players have If the voltage at the IN pin exceeds 5.8V (VIN(OV)), highly integrated subsystems fabricated from deep submi- GATE is pulled low quickly to protect the load. The cron CMOS processes. The small form factor is accompa- incoming power supply must remain below 5.7V nied by low absolute maximum voltage ratings. The sensi- (VIN(OV) – ∆VOV) for the duration of the start-up delay to tive electronics are susceptible to damage from transient or restart the GATE ramp-up. DC overvoltage conditions from the power supply. A sense resistor placed between IN and SENSE imple- Failures or faults in the power adaptor can cause an overvolt- ments an overcurrent protection with a 50mV trip age event. So can hot-plugging an AC adaptor into the power threshold and a 10µs glitch filter. After an overcurrent, input of the mobile device (see ADI Application Note 88). the LTC4361-1 latches off while the LTC4361-2 restarts Today’s mobile devices derive their power supply or recharge following a 130ms delay. their internal batteries from multiple alternative inputs like AC The LTC4361 has a CMOS compatible ON input. When wall adaptors, car battery adaptors and USB ports. A user driven low, the part is enabled. When driven high, the may unknowingly plug in the wrong adaptor, damaging the external N-channel MOSFET is turned off and the supply device with a high or even a negative power supply voltage. current of the LTC4361 drops to 1.5µA. The PWRGD pull- The LTC4361 protects low voltage electronics from these down releases during this low current sleep mode, UVLO, overvoltage conditions by controlling a low cost external overvoltage or overcurrent and the subsequent 130ms N-channel MOSFET configured as a pass transistor. At start-up delay. After the start-up delay, GATE starts its power-up (VIN > 2.1V), a start-up delay cycle begins. Any slow ramp-up and ramps higher than VGATE(TH) to trigger overvoltage condition causes the delay cycle to continue a 65ms delay cycle. When that completes, PWRGD pulls until a safe voltage is present. When the delay cycle com- low. The LTC4361 has a GATEP pin that drives an optional pletes, an internal high side switch driver slowly ramps up external P-channel MOSFET to provide protection against the MOSFET gate, powering up the output at a controlled negative voltages at IN. rate and limiting the inrush current to the output capacitor. Rev C 6 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts