Datasheet LTM4601HV (Analog Devices) - 7

LTM4601HV
PIN FUNCTIONS (See Package Description for Pin Assignment) VIN (Bank 1):
Power Input Pins. Apply input voltage be-
TRACK/SS (Pin A9):
Output Voltage Tracking and Soft- tween these pins and PGND pins. Recommend placing Start Pin. When the module is configured as a master input decoupling capacitance directly between VIN pins output, then a soft-start capacitor is placed on this pin and PGND pins. to ground to control the master ramp rate. A soft-start
V
capacitor can be used for soft-start turn on of a stand
OUT (Bank 3):
Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing alone regulator. Slave operation is performed by putting output decoupling capacitance directly between these pins a resistor divider from the master output to ground, and and PGND pins. See Figure 17. connecting the center point of the divider to this pin. See the Applications Information section.
PGND (Bank 2):
Power ground pins for both input and output returns.
MPGM (Pin A12):
Programmable Margining Input. A re- sistor from this pin to ground sets a current that is equal
V – OSNS (Pin M12):
(–) Input to the Remote Sense Ampli- to 1.18V/R. This current multiplied by 10kW will equal a fier. This pin connects to the ground remote sense point. value in millivolts that is a percentage of the 0.6V refer- The remote sense amplifier is used for VOUT ≤3.3V. Tie to ence voltage. See Applications Information. To parallel INTVCC if not used. LTM4601HVs, each requires an individual MPGM resistor.
V + OSNS (Pin J12):
(+) Input to the Remote Sense Ampli- Do not tie MPGM pins together. fier. This pin connects to the output remote sense point.
fSET (Pin B12):
Frequency Set Internally to 850kHz. An The remote sense amplifier is used for VOUT ≤3.3V. Tie to external resistor can be placed from this pin to ground ground if not used. to increase frequency. See the Applications Information
DIFFVOUT (Pin K12):
Output of the Remote Sense Ampli- section for frequency adjustment. fier. This pin connects to the VOUT_LCL pin. Leave floating
VFB (Pin F12):
The Negative Input of the Error Amplifier. if remote sense amplifier is not used. Internally, this pin is connected to VOUT_LCL pin with a
DRVCC (Pin E12):
This pin normally connects to INTVCC 60.4k precision resistor. Different output voltages can be for powering the internal MOSFET drivers. This pin can be programmed with an additional resistor between VFB and biased up to 6V from an external supply with about 50mA SGND pins. See the Applications Information section. capability, or an external circuit as shown in Figure 18.
MARG0 (Pin C12):
This pin is the LSB logic input for the This improves efficiency at the higher input voltages by margining function. Together with the MARG1 pin it will reducing power dissipation in the module. determine if margin high, margin low or no margin state
INTVCC (Pin A7):
This pin is for additional decoupling of is applied. The pin has an internal pull-down resistor of the 5V internal regulator. 50k. See the Applications Information section.
PLLIN (Pin A8):
External Clock Synchronization Input
MARG1 (Pin D12):
This pin is the MSB logic input for the to the Phase Detector. This pin is internally terminated margining function. Together with the MARG0 pin it will to SGND with a 50k resistor. Apply a clock with a high determine if margin high, margin low or no margin state level above 2V and below INTVCC. See the Applications is applied. The pin has an internal pull-down resistor of Information section. 50k. See the Applications Information section. 4601hvfb 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photos Related Parts