Datasheet LTM4602 (Analog Devices) - 9

LTM4602
APPLICATIONS INFORMATION
The typical LTM4602 application circuit is shown in Fig- voltage VOUT needs to be margined up/down by ±M%, ure 21. External component selection is primarily deter- the resistor values of RUP and RDOWN can be calculated mined by the maximum load current and output voltage. from the following equations:
Output Voltage Programming and Margining
(RSET RUP)• VOUT •(1+M%) =0.6V (R The PWM controller of the LTM4602 has an internal SET RUP) + 100k 0.6V reference voltage. As shown in the block diagram, R a 100k/0.5% internal feedback resistor connects V SET • VOUT •(1– M%) OUT = 0.6V and V R OSET pins. Adding a resistor RSET from VOSET pin to SET + (100k RDOWN) SGND pin programs the output voltage:
Input Capacitors
100k +R V SET OUT = 0.6V • R The LTM4602 μModule should be connected to a low SET AC-impedance DC source. High frequency, low ESR input Table 1 shows the standard values of 1% RSET resistor capacitors are required to be placed adjacent to the mod- for typical output voltages: ule. In Figure 21, the bulk input capacitor CIN is selected
Table 1
for its ability to handle the large RMS current into the
R
converter. For a buck converter, the switching duty cycle
SET
Open 100 66.5 49.9 43.2 31.6 22.1 13.7
(k
Ω
)
can be estimated as:
VOUT
0.6 1.2 1.5 1.8 2 2.5 3.3 5
(V)
D= VOUT Voltage margining is the dynamic adjustment of the output VIN voltage to its worst case operating range in production Without considering the inductor current ripple, the RMS testing to stress the load circuitry, verify control/protec- current of the input capacitor can be estimated as: tion functionality of the board and improve the system reliability. Figure 2 shows how to implement margining I function with the LTM4602. In addition to the feedback I OUT(MAX) CIN(RMS) = • D •(1D) % resistor RSET, several external components are added. Turn off both transistor Q In the above equation, UP and QDOWN to disable the η% is the estimated effi ciency of margining. When Q the power module. C1 can be a switcher-rated electrolytic UP is on and QDOWN is off, the output voltage is margined up. The output voltage is margined aluminum capacitor, OS-CON capacitor or high volume down when Q ceramic capacitors. Note the capacitor ripple current DOWN is on and QUP is off. If the output ratings are often based on only 2000 hours of life. This VOUT LTM4602 makes it advisable to properly derate the input capacitor, RDOWN or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for 100k QDOWN derating requirements. V 2N7002 OSET In Figure 21, the input capacitors are used as high frequency PGND SGND input decoupling capacitors. In a typical 6A output applica- RSET RUP tion, 1-2 pieces of very low ESR X5R or X7R, 10μF ceramic capacitors are recommended. This decoupling capacitor QUP should be placed directly adjacent the module input pins 2N7002 in the PCB layout to minimize the trace inductance and 4602 F02
Figure 2. LTM4602 Margining Implementation
high frequency AC noise. 4602fa 9