Datasheet LTM4602HV (Analog Devices) - 9

LTM4602HV
U U W U APPLICATIO S I FOR ATIO
The typical LTM4602HV application circuit is shown in voltage is margined up. The output voltage is margined Figure 20. External component selection is primarily down when QDOWN is on and QUP is off. If the output determined by the maximum load current and output voltage VO needs to be margined up/down by ±M%, the voltage. resistor values of RUP and RDOWN can be calculated from the following equations:
Output Voltage Programming and Margining
(R R )•V •(1+ % M ) SET UP O The PWM controller of the LTM4602HV has an internal = . 0 V 6 (R R )+ k 100 Ω 0.6V±1% reference voltage. As shown in the block diagram, SET UP a 100k/0.5% internal feedback resistor connects VOUT and R •V •( – 1 M FB pins. Adding a resistor R SET O %) SET from VOSET pin to SGND = . 0 V 6 pin programs the output voltage: R + ( k 100 Ω R ) SET DOWN k 100 R V = + 0. V SET O 6 •
Input Capacitors
RSET The LTM4602HV µModule should be connected to a low Table 1 shows the standard values of 1% RSET resistor ac-impedance DC source. High frequency, low ESR input for typical output voltages: capacitors are required to be placed adjacent to the mod-
Table 1
ule. In Figure 20, the bulk input capacitor CIN is selected
R
for its ability to handle the large RMS current into the
SET
Open 100 66.5 49.9 43.2 31.6 22.1 13.7
(k
Ω
)
converter. For a buck converter, the switching duty-cycle
VO
can be estimated as: 0.6 1.2 1.5 1.8 2 2.5 3.3 5
(V)
V Voltage margining is the dynamic adjustment of the output D O = voltage to its worst case operating range in production VIN testing to stress the load circuitry, verify control/protec- Without considering the inductor current ripple, the RMS tion functionality of the board and improve the system current of the input capacitor can be estimated as: reliability. Figure 2 shows how to implement margining function with the LTM4602HV. In addition to the feedback I I O M ( AX) = • D •( − 1 D CIN RMS ( ) resistor RSET, several external components are added. % η Turn off both transistor QUP and QDOWN to disable the margining. When Q In the above equation, UP is on and QDOWN is off, the output η% is the estimated effi ciency of the power module. C1 can be a switcher-rated electrolytic V aluminum capacitor, OS-CON capacitor or high volume OUT LTM4602HV ceramic capacitors. Note the capacitor ripple current RDOWN ratings are often based on only 2000 hours of life. This 100k makes it advisable to properly derate the input capacitor, QDOWN or choose a capacitor rated at a higher temperature than V 2N7002 OSET required. Always contact the capacitor manufacturer for PGND SGND derating requirements. RSET RUP In Figure 16, the input capacitors are used as high frequency QUP input decoupling capacitors. In a typical 6A output applica- 2N7002 tion, 1-2 pieces of very low ESR X5R or X7R, 10µF ceramic 4602HV F02 capacitors are recommended. This decoupling capacitor
Figure 2
should be placed directly adjacent the module input pins 4602hvf 9