Datasheet LTM4608A (Analog Devices) - 7

LTM4608A
PIN FUNCTIONS VIN (C1, C8, C9, D1, D3-D5, D7-D9 and E8):
Power Input
PLLLPF (E3):
Phase Locked Loop Lowpass Filter. An in- Pins. Apply input voltage between these pins and GND ternal lowpass filter is tied to this pin. In spread spectrum pins. Recommend placing input decoupling capacitance mode, placing a capacitor here to SGND controls the slew directly between VIN pins and GND pins. rate from one frequency to the next. Alternatively, floating this pin allows normal running frequency at 1.5MHz, tying
VOUT (C10-C11, D10-D11, E9-E11, F9-F11, G9-G11):
this pin to SVIN forces the part to run at 1.33 times its Power Output Pins. Apply output load between these pins normal frequency (2MHz), tying it to ground forces the and GND pins. Recommend placing output decoupling frequency to run at 0.67 times its normal frequency (1MHz). capacitance directly between these pins and GND pins. See Table 1.
PHMODE (B4):
Phase Selector Input. This pin determines the phase relationship between the internal oscillator and
GND (A1-A11, B1, B9-B11, F3, F7-F8, G1-G8):
Power CLKOUT. Tie it high for 2-phase operation, tie it low for Ground Pins for Both Input and Output Returns. 3-phase operation, and float or tie it to VIN/2 for 4-phase
SVIN (F4):
Signal Input Voltage. This pin is internally con- operation. nected to VIN through a lowpass filter.
MGN (B8):
Margining Pin. Increases or decreases the
SGND (E1):
Signal Ground Pin. Return ground path for all output voltage by the amount specified by the BSEL pin. analog and low power circuitry. Tie a single connection to To disable margining, tie the MGN pin to a voltage divider GND in the application. with 50k resistors from VIN to ground. See the Applications Information section and Figure 20.
MODE (B5):
Mode Select Input. Tying this pin high enables Burst Mode operation. Tying this pin low enables forced
BSEL (B7):
Margining Bit Select Pin. Tying BSEL low se- continuous operation. Floating this pin or tying it to VIN/2 lects ±5%, tying it high selects ±10%. Floating it or tying enables pulse-skipping operation. it to VIN/2 selects ±15%.
CLKIN (B3):
External Synchronization Input to Phase
TRACK (E5):
Output Voltage Tracking Pin. Voltage track- Detector. This pin is internally terminated to SGND with a ing is enabled when the TRACK voltage is below 0.57V. 50k resistor. The phase locked loop will force the internal If tracking is not desired, then connect the TRACK pin to top power PMOS turn on to be synchronized with the SVIN. If TRACK is not tied to SVIN, then the TRACK pin’s rising edge of the CLKIN signal. Connect this pin to SVIN voltage needs to be below 0.18V before the chip shuts to enable spread spectrum modulation. During external down even though RUN is already low. Do not float this synchronization, make sure the PLLLPF pin is not tied to pin. A resistor divider and capacitor can be applied to the VIN or GND. TRACK pin to increase the soft-start time of the regulator. See the Applications Information section. Can tie together for parallel operation and tracking. Load current needs to be present during track down. 4608afe For more information www.linear.com/LTM4608A 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Typical Performance Characteristics Pin Functions Simplified Block Diagram Operation Applications Information Typical Applications Package Description Package Photo Revision History Package Description Related Parts