Datasheet LTM8031 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Ultralow Noise EMC 36V, 1A DC/DC µModule Regulator |
| Páginas / Página | 22 / 7 — pin FuncTions. SYNC (Pin L6):. ADJ (Pin J7):. PGOOD (Pin K7):. block … |
| Formato / tamaño de archivo | PDF / 304 Kb |
| Idioma del documento | Inglés |
pin FuncTions. SYNC (Pin L6):. ADJ (Pin J7):. PGOOD (Pin K7):. block DiagraM
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LTM8031
pin FuncTions SYNC (Pin L6):
This is the external clock synchronization The PGOOD output is valid when VIN is above 3.6V and input. Ground this pin for low ripple Burst Mode® operation RUN/SS is high. If this function is not used, leave this at low output loads. Tie to a stable voltage source greater pin floating. than 0.7V to disable Burst Mode operation. Do not leave
ADJ (Pin J7):
The LTM8031 regulates its ADJ pin to 0.79V. this pin floating. Tie to a clock source for synchroniza- Connect the adjust resistor from this pin to ground. The tion. Clock edges should have rise and fall times faster value of R than 1µs. See Synchronization section in Applications ADJ is given by the equation: Information. 196.71 RADJ =
PGOOD (Pin K7):
The PGOOD pin is the open-collector VOUT – 0.79 output of an internal comparator. PGOOD remains low until where R the ADJ pin is within 10% of the final regulation voltage. ADJ is in kΩ.
block DiagraM
FIN EMI FILTER 4.7µH V V IN OUT AUX 22pF 249k 10µF GND GND BIAS SHARE CURRENT MODE CONTROLLER RUN/SS SYNC RT PGOOD ADJ 8031 BD 8031fb 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical application Related Parts
pin FuncTions SYNC (Pin L6):
This is the external clock synchronization The PGOOD output is valid when VIN is above 3.6V and input. Ground this pin for low ripple Burst Mode® operation RUN/SS is high. If this function is not used, leave this at low output loads. Tie to a stable voltage source greater pin floating. than 0.7V to disable Burst Mode operation. Do not leave
ADJ (Pin J7):
The LTM8031 regulates its ADJ pin to 0.79V. this pin floating. Tie to a clock source for synchroniza- Connect the adjust resistor from this pin to ground. The tion. Clock edges should have rise and fall times faster value of R than 1µs. See Synchronization section in Applications ADJ is given by the equation: Information. 196.71 RADJ =
PGOOD (Pin K7):
The PGOOD pin is the open-collector VOUT – 0.79 output of an internal comparator. PGOOD remains low until where R the ADJ pin is within 10% of the final regulation voltage. ADJ is in kΩ.
block DiagraM
FIN EMI FILTER 4.7µH V V IN OUT AUX 22pF 249k 10µF GND GND BIAS SHARE CURRENT MODE CONTROLLER RUN/SS SYNC RT PGOOD ADJ 8031 BD 8031fb 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical application Related Parts