Datasheet LTM8033 (Analog Devices) - 8

LTM8033
PIN FUNCTIONS VOUT (Bank 1):
Power Output Pins. Apply the output filter
SYNC (Pin B8):
This is the external clock synchronization capacitor and the output load between these pins and input. Ground this pin for low ripple Burst Mode® operation GND pins. at low output loads. Tie to a stable voltage source greater
GND (A8, Bank 2):
Tie these GND pins to a local ground than 0.7V to disable Burst Mode operation. Do not leave plane below the LTM8033 and the circuit components. this pin floating. Tie to a clock source for synchronization. Return the feedback divider (R Clock edges should have rise and fall times faster than ADJ) to this net. 1μs. See the Synchronization section in the Applications
FIN (Bank 3):
Filtered Input. This is the node after the input Information section. EMI filter. Apply the capacitor recommended by Table 1. Additional capacitance may be applied if there is a need
PGOOD (Pin B7):
The PGOOD pin is the open-collector to modify the behavior of the integrated EMI filter; other- output of an internal comparator. PGOOD remains low wise, leave these pins unconnected. See the Applications until the ADJ pin is greater than 90% of the final regulation Information section for more details. voltage. PGOOD output is valid when VIN is above 3.6V and RUN/SS is high. If this function is not used, leave
VIN (Bank 4):
The VIN pin supplies current to the LTM8033’s this pin floating. internal regulator and to the internal power switch. This pin must be locally bypassed with an external, low ESR
AUX (Pin G3):
Low Current Voltage Source for BIAS. capacitor; see Table 1 for recommended values. Ensure In many designs, the BIAS pin is simply connected to that V VOUT. The AUX pin is internally connected to VOUT and IN + BIAS is less than 56V. is placed adjacent to the BIAS pin to ease printed circuit
SHARE (Pin A6):
Tie this to the SHARE pin of another board routing. Although this pin is internally connected LTM8033 when paralleling the outputs. Otherwise, do to VOUT, it is not intended to deliver a high current, so do not connect.
not
connect this pin to the load. If this pin is not tied to
ADJ (Pin A7):
The LTM8033 regulates its ADJ pin to 0.79V. BIAS, leave it floating. Connect the adjust resistor from this pin to ground. The
BIAS (Pin G4):
The BIAS pin connects to the internal power value of RADJ is given by the equation RADJ = 394.21/(VOUT bus. Connect to a power source greater than 2.8V and less – 0.79), where RADJ is in kΩ. than 25V. If the output is greater than 2.8V, connect this
RT (Pin B6):
The RT pin is used to program the switching pin there. If the output voltage is less, connect this to a frequency of the LTM8033 by connecting a resistor from voltage source between 2.8V and 25V but ensure that VIN this pin to ground. The Applications Information section of + BIAS is less than 56V. the data sheet includes a table to determine the resistance
RUN/SS (Pin G8):
Pull the RUN/SS pin below 0.2V to value based on the desired switching frequency. Minimize shut down the LTM8033. Tie to 2.5V or more for normal capacitance at this pin. operation. If the shutdown feature is not used, tie this pin to the VIN pin. RUN/SS also provides a soft-start function; see the Applications Information section. 8033fb 8 For more information www.linear.com/LTM8033 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Photographs Revision History Typical Application Related Parts