Datasheet LTM4653 (Analog Devices) - 8

link to page 16 link to page 16 link to page 16 LTM4653
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN (F4):
Run Control Pin. A voltage above 1.2V com-
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
mands the Module to regulate its output voltage. Under-
LAYOUT CAREFULLY.
voltage lockout (UVLO) can be implemented by connecting
VIN (A1-A3, B3):
Power Input Pins. Apply input voltage RUN to the midpoint node formed by a resistor-divider and input decoupling capacitance directly between VIN between VIN and GND. RUN features 130mV of hysteresis. and a ground (PGND) plane. See the Applications Information section.
VD (A4, B4, C4):
Drain of the Converter’s Primary Switch-
INTVCC (G3):
Internal Regulator, 3.3V Nominal Output. ing MOSFET. Apply at minimum one 4.7µF high frequency Internal control circuits and MOSFET-drivers derive pow- ceramic decoupling capacitor directly from VD to PGND. er from INTVCC bias. When operating 3.1V < SVIN ≤ 58V, Give this capacitor higher layout priority (closer proximity an LDO generates INTVCC from SVIN when RUN is logic to the module) than any VIN decoupling capacitors. high (RUN > 1.2V). No external decoupling is required.
SV
When RUN is logic low (RUN - GND < 1.2V), the INTV
IN (C3):
Input Voltage Supply for Small-Signal Circuits. CC SV LDO is off, i.e., INTV IN is the input to the INTVCC LDO. Connect SVIN directly CC is unregulated. (Also see EXTVCC.) to VIN. No decoupling capacitor is needed on this pin.
EXTVCC (F3):
External Bias, Auxiliary Input to the INTVCC
PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-5, K4-
Regulator. When EXTVCC exceeds 3.2V and SVIN exceeds
5, L4-5):
Power Ground Pins of the LTM4653. Connect 5V, the INTVCC LDO derives power from EXTVCC bias all pins to the application’s PGND plane. instead of the SVIN path. This technique can reduce LDO losses considerably, resulting in a corresponding reduc-
VOUT (K1-3, L1-3):
Power Output Pins of the LTM4653. tion in module junction temperature. For applications in Connect all pins to the application’s power VOUT plane. Apply which 4V ≤ V the output filter capacitors and the output load between OUT ≤ 26.5V, connect EXTVCC to VOUT through a resistor. (See the Applications Information section for a power VOUT plane and the application’s PGND plane. resistor value.) When taking advantage of this EXTVCC
GND (D4):
Ground Pin of the LTM4653. Electrically con- feature, locally decouple EXTVCC to PGND with a 1µF ce- nect to the application’s PGND plane. ramic—otherwise, leave EXTVCC open circuit.
VOSNS (G1, H1):
Output Voltage Sense and Feedback Signal.
ISETb (F1):
1.5nF Soft-Start Capacitor. Connect ISETb Connect VOSNS to VOUT at the point of load (POL). Pins G1 to ISETa to achieve default soft-start characteristics, if and H1 are electrically connected to each other internal to desired. See ISETa. the module, and thus it is only necessary to connect one
ISETa (F2):
Accurate 50μA Current Source. Positive input VOSNS pin to VOUT at the POL. The remaining VOSNS pin to the error amplifier. Connect a resistor (R can be used for redundant connectivity or routed to an ICT ISET) from this pin to SGND to program the desired LTM4653 output volt- test point for design-for-test considerations, as desired. age, VOUT = RISET • 50μA. A capacitor can be connected
SGND (E4, G2, H2):
Signal Ground Pins of the LTM4653. from ISETa to SGND to soft-start the output voltage and Connect Pin H2 to PGND directly under the LTM4653. The reduce start-up inrush current. Connect ISETa to ISETb in SGND pins at locations E4 and G2 are electrically con- order to achieve default soft-start, if desired. (See ISETb.) nected to each other internal to the module, and thus it is In addition, the output of the LTM4653 can track a voltage only necessary to connect one SGND pin to PGND under applied between the ISETa pin and the SGND pins. (See the module. The remaining SGND pins can be used for the Applications Information section.) redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. Rev 0 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Test Circuit Decoupling Requirements Operation Operation Operation Applications Information Typical Applications Package Photograph Package Description Typical Application Related Parts