Datasheet ADuM6410, ADuM6411, ADuM6412 (Analog Devices) - 7

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Data Sheet ADuM6410/ADuM6411/ADuM6412 ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = 5.0 V, VISO = 3.3 V, VSEL resistor network: R1 = 10 kΩ ± 1%, R2 = 16.9 kΩ ± 1% between VISO and GNDISO (see Figure 31). Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1 = VDDP ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 11. DC-to-DC Converter Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY Setpoint VISO 3.0 3.3 3.6 V IISO = 15 mA, R1 = 10 kΩ, R2 = 16.9 kΩ Line Regulation VISO (LINE) 20 mV/V IISO = 15 mA, VDD1 = 3.0 V to 3.6 V Load Regulation VISO (LOAD) 1 5 % IISO = 3 mA to 27 mA Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF||10 µF, IISO = 27 mA Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF||10 µF, IISO = 27 mA Switching Frequency fOSC 125 MHz Pulse-Width Modulation Frequency fPWM 600 kHz Output Supply IISO (MAX) 30 mA 3.6 V > VISO > 3 V Efficiency at IISO (MAX) 24 % IISO = 27 mA VDDP Supply Current No VISO Load IDDP (Q) 14 20 mA Full VISO Load IDDP (MAX) 85 115 mA Thermal Shutdown Shutdown Temperature 154 °C Thermal Hysteresis 10 °C
Table 12. Data Channel Supply Current Specifications 1 Mbps 25 Mbps 100 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT CL = 0 pF ADuM6410 IDD1 6.8 10 7.8 12 11.8 17.4 mA IDD2 2.0 3.7 3.5 5.5 8.2 11.6 mA ADuM6411 IDD1 5.8 10.3 7.0 10.9 11.4 15.9 mA IDD2 3.9 6.65 5.2 8.0 9.4 12.8 mA ADuM6412 IDD1 4.3 7.7 6.0 9.3 10.3 14.2 mA IDD2 5.0 8.4 6.2 9.6 9.8 13.7 mA
Table 13. Switching Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS Data Rate 150 Mbps Within PWD limit Propagation Delay tPHL, tPLH 6.8 14 ns 50% input to 50% output Pulse Width Distortion PWD 0.7 3.0 ns |tPLH − tPHL| Pulse Width PW 6.7 ns Within PWD limit Propagation Delay Skew tPSK 7.5 ns Between any two units at the same temperature, voltage, and load Channel Matching Codirectional tPSKCD 0.7 3.0 ns Opposing Direction tPSKOD 0.7 3.0 ns Jitter 640 ps p-p 75 ns rms Rev. 0 | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLES TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY RELATED PARAMETERS EMI CONSIDERATIONS POWER CONSUMPTION INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example OUTLINE DIMENSIONS ORDERING GUIDE