Datasheet ATtiny25/V, ATtiny45/V, ATtiny85/V. Complete (Atmel) - 10

link to page 10 link to page 10 link to page 11
4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor- mance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2.
AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are sin- gle cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
4.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. ATtiny25/45/85 [DATASHEET] 10 2586Q–AVR–08/2013 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 4. AVR CPU Core 4.1 Introduction 4.2 Architectural Overview 4.3 ALU – Arithmetic Logic Unit 4.4 Status Register 4.4.1 SREG – AVR Status Register 4.5 General Purpose Register File 4.5.1 The X-register, Y-register, and Z-register 4.6 Stack Pointer 4.6.1 SPH and SPL — Stack Pointer Register 4.7 Instruction Execution Timing 4.8 Reset and Interrupt Handling 4.8.1 Interrupt Response Time 5. AVR Memories 5.1 In-System Re-programmable Flash Program Memory 5.2 SRAM Data Memory 5.2.1 Data Memory Access Times 5.3 EEPROM Data Memory 5.3.1 EEPROM Read/Write Access 5.3.2 Atomic Byte Programming 5.3.3 Split Byte Programming 5.3.4 Erase 5.3.5 Write 5.3.6 Preventing EEPROM Corruption 5.4 I/O Memory 5.5 Register Description 5.5.1 EEARH – EEPROM Address Register 5.5.2 EEARL – EEPROM Address Register 5.5.3 EEDR – EEPROM Data Register 5.5.4 EECR – EEPROM Control Register 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution 6.1.1 CPU Clock – clkCPU 6.1.2 I/O Clock – clkI/O 6.1.3 Flash Clock – clkFLASH 6.1.4 ADC Clock – clkADC 6.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK 6.1.6 Internal PLL in ATtiny15 Compatibility Mode 6.2 Clock Sources 6.2.1 External Clock 6.2.2 High Frequency PLL Clock 6.2.3 Calibrated Internal Oscillator 6.2.4 Internal 128 kHz Oscillator 6.2.5 Low-Frequency Crystal Oscillator 6.2.6 Crystal Oscillator / Ceramic Resonator 6.2.7 Default Clock Source 6.3 System Clock Prescaler 6.3.1 Switching Time 6.4 Clock Output Buffer 6.5 Register Description 6.5.1 OSCCAL – Oscillator Calibration Register 6.5.2 CLKPR – Clock Prescale Register 7. Power Management and Sleep Modes 7.1 Sleep Modes 7.1.1 Idle Mode 7.1.2 ADC Noise Reduction Mode 7.1.3 Power-down Mode 7.2 Software BOD Disable 7.2.1 Limitations 7.3 Power Reduction Register 7.4 Minimizing Power Consumption 7.4.1 Analog to Digital Converter 7.4.2 Analog Comparator 7.4.3 Brown-out Detector 7.4.4 Internal Voltage Reference 7.4.5 Watchdog Timer 7.4.6 Port Pins 7.5 Register Description 7.5.1 MCUCR – MCU Control Register 7.5.2 PRR – Power Reduction Register 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.2.1 Power-on Reset 8.2.2 External Reset 8.2.3 Brown-out Detection 8.2.4 Watchdog Reset 8.3 Internal Voltage Reference 8.3.1 Voltage Reference Enable Signals and Start-up Time 8.4 Watchdog Timer 8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer 8.4.1.1 Safety Level 1 8.4.1.2 Safety Level 2 8.4.2 Code Example 8.5 Register Description 8.5.1 MCUSR – MCU Status Register 8.5.2 WDTCR – Watchdog Timer Control Register 9. Interrupts 9.1 Interrupt Vectors in ATtiny25/45/85 9.2 External Interrupts 9.2.1 Low Level Interrupt 9.2.2 Pin Change Interrupt Timing 9.3 Register Description 9.3.1 MCUCR – MCU Control Register 9.3.2 GIMSK – General Interrupt Mask Register 9.3.3 GIFR – General Interrupt Flag Register 9.3.4 PCMSK – Pin Change Mask Register 10. I/O Ports 10.1 Introduction 10.2 Ports as General Digital I/O 10.2.1 Configuring the Pin 10.2.2 Toggling the Pin 10.2.3 Switching Between Input and Output 10.2.4 Reading the Pin Value 10.2.5 Digital Input Enable and Sleep Modes 10.2.6 Unconnected Pins 10.3 Alternate Port Functions 10.3.1 Alternate Functions of Port B 10.4 Register Description 10.4.1 MCUCR – MCU Control Register 10.4.2 PORTB – Port B Data Register 10.4.3 DDRB – Port B Data Direction Register 10.4.4 PINB – Port B Input Pins Address 11. 8-bit Timer/Counter0 with PWM 11.1 Features 11.2 Overview 11.2.1 Registers 11.2.2 Definitions 11.3 Timer/Counter0 Prescaler and Clock Sources 11.3.1 Internal Clock Source with Prescaler 11.3.2 Prescaler Reset 11.3.3 External Clock Source 11.4 Counter Unit 11.5 Output Compare Unit 11.5.1 Force Output Compare 11.5.2 Compare Match Blocking by TCNT0 Write 11.5.3 Using the Output Compare Unit 11.6 Compare Match Output Unit 11.6.1 Compare Output Mode and Waveform Generation 11.7 Modes of Operation 11.7.1 Normal Mode 11.7.2 Clear Timer on Compare Match (CTC) Mode 11.7.3 Fast PWM Mode 11.7.4 Phase Correct PWM Mode 11.8 Timer/Counter Timing Diagrams 11.9 Register Description 11.9.1 GTCCR – General Timer/Counter Control Register 11.9.2 TCCR0A – Timer/Counter Control Register A 11.9.3 TCCR0B – Timer/Counter Control Register B 11.9.4 TCNT0 – Timer/Counter Register 11.9.5 OCR0A – Output Compare Register A 11.9.6 OCR0B – Output Compare Register B 11.9.7 TIMSK – Timer/Counter Interrupt Mask Register 11.9.8 TIFR – Timer/Counter Interrupt Flag Register 12. 8-bit Timer/Counter1 12.1 Timer/Counter1 Prescaler 12.2 Counter and Compare Units 12.2.1 Timer/Counter1 Initialization for Asynchronous Mode 12.2.2 Timer/Counter1 in PWM Mode 12.3 Register Description 12.3.1 TCCR1 – Timer/Counter1 Control Register 12.3.2 GTCCR – General Timer/Counter1 Control Register 12.3.3 TCNT1 – Timer/Counter1 12.3.4 OCR1A –Timer/Counter1 Output Compare RegisterA 12.3.5 OCR1B – Timer/Counter1 Output Compare RegisterB 12.3.6 OCR1C – Timer/Counter1 Output Compare RegisterC 12.3.7 TIMSK – Timer/Counter Interrupt Mask Register 12.3.8 TIFR – Timer/Counter Interrupt Flag Register 12.3.9 PLLCSR – PLL Control and Status Register 13. 8-bit Timer/Counter1 in ATtiny15 Mode 13.1 Timer/Counter1 Prescaler 13.2 Counter and Compare Units 13.2.1 Timer/Counter1 in PWM Mode 13.3 Register Description 13.3.1 TCCR1 – Timer/Counter1 Control Register 13.3.2 GTCCR – General Timer/Counter1 Control Register 13.3.3 TCNT1 – Timer/Counter1 13.3.4 OCR1A – Timer/Counter1 Output Compare RegisterA 13.3.5 OCR1C – Timer/Counter1 Output Compare Register C 13.3.6 TIMSK – Timer/Counter Interrupt Mask Register 13.3.7 TIFR – Timer/Counter Interrupt Flag Register 13.3.8 PLLCSR – PLL Control and Status Register 14. Dead Time Generator 14.1 Register Description 14.1.1 DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1 14.1.2 DT1A – Timer/Counter1 Dead Time A 14.1.3 DT1B – Timer/Counter1 Dead Time B 15. USI – Universal Serial Interface 15.1 Features 15.2 Overview 15.3 Functional Descriptions 15.3.1 Three-wire Mode 15.3.2 SPI Master Operation Example 15.3.3 SPI Slave Operation Example 15.3.4 Two-wire Mode 15.3.5 Start Condition Detector 15.3.6 Clock speed considerations 15.4 Alternative USI Usage 15.4.1 Half-Duplex Asynchronous Data Transfer 15.4.2 4-Bit Counter 15.4.3 12-Bit Timer/Counter 15.4.4 Edge Triggered External Interrupt 15.4.5 Software Interrupt 15.5 Register Descriptions 15.5.1 USIDR – USI Data Register 15.5.2 USIBR – USI Buffer Register 15.5.3 USISR – USI Status Register 15.5.4 USICR – USI Control Register 16. Analog Comparator 16.1 Analog Comparator Multiplexed Input 16.2 Register Description 16.2.1 ADCSRB – ADC Control and Status Register B 16.2.2 ACSR – Analog Comparator Control and Status Register 16.2.3 DIDR0 – Digital Input Disable Register 0 17. Analog to Digital Converter 17.1 Features 17.2 Overview 17.3 Operation 17.4 Starting a Conversion 17.5 Prescaling and Conversion Timing 17.6 Changing Channel or Reference Selection 17.6.1 ADC Input Channels 17.6.2 ADC Voltage Reference 17.7 ADC Noise Canceler 17.8 Analog Input Circuitry 17.9 Noise Canceling Techniques 17.10 ADC Accuracy Definitions 17.11 ADC Conversion Result 17.11.1 Single Ended Conversion 17.11.2 Unipolar Differential Conversion 17.11.3 Bipolar Differential Conversion 17.12 Temperature Measurement 17.13 Register Description 17.13.1 ADMUX – ADC Multiplexer Selection Register 17.13.2 ADCSRA – ADC Control and Status Register A 17.13.3 ADCL and ADCH – The ADC Data Register 17.13.3.1 ADLAR = 0 17.13.3.2 ADLAR = 1 17.13.4 ADCSRB – ADC Control and Status Register B 17.13.5 DIDR0 – Digital Input Disable Register 0 18. debugWIRE On-chip Debug System 18.1 Features 18.2 Overview 18.3 Physical Interface 18.4 Software Break Points 18.5 Limitations of debugWIRE 18.6 Register Description 18.6.1 DWDR – debugWire Data Register 19. Self-Programming the Flash 19.1 Performing Page Erase by SPM 19.2 Filling the Temporary Buffer (Page Loading) 19.3 Performing a Page Write 19.4 Addressing the Flash During Self-Programming 19.5 EEPROM Write Prevents Writing to SPMCSR 19.6 Reading Lock, Fuse and Signature Data from Software 19.6.1 Reading Lock Bits from Firmware 19.6.2 Reading Fuse Bits from Firmware 19.6.3 Reading Device Signature Imprint Table from Firmware 19.7 Preventing Flash Corruption 19.8 Programming Time for Flash when Using SPM 19.9 Register Description 19.9.1 SPMCSR – Store Program Memory Control and Status Register 20. Memory Programming 20.1 Program And Data Memory Lock Bits 20.2 Fuse Bytes 20.2.1 Latching of Fuses 20.3 Device Signature Imprint Table 20.3.1 Signature Bytes 20.3.2 Calibration Bytes 20.4 Page Size 20.5 Serial Downloading 20.5.1 Serial Programming Algorithm 20.5.2 Serial Programming Instruction set 20.6 High-voltage Serial Programming 20.7 High-voltage Serial Programming Algorithm 20.7.1 Enter High-voltage Serial Programming Mode 20.7.2 Considerations for Efficient Programming 20.7.3 Chip Erase 20.7.4 Programming the Flash 20.7.5 Programming the EEPROM 20.7.6 Reading the Flash 20.7.7 Reading the EEPROM 20.7.8 Programming and Reading the Fuse and Lock Bits 20.7.9 Reading the Signature Bytes and Calibration Byte 20.7.10 Power-off sequence 21. Electrical Characteristics 21.1 Absolute Maximum Ratings* 21.2 DC Characteristics 21.3 Speed 21.4 Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy 21.4.2 External Clock Drive 21.5 System and Reset Characteristics 21.5.1 Standard Power-On Reset 21.5.2 Enhanced Power-On Reset 21.6 Brown-Out Detection 21.7 ADC Characteristics 21.8 Serial Programming Characteristics 21.9 High-voltage Serial Programming Characteristics 22. Typical Characteristics 22.1 Active Supply Current 22.2 Idle Supply Current 22.3 Supply Current of I/O modules 22.3.1 Example 22.4 Power-down Supply Current 22.5 Pin Pull-up 22.6 Pin Driver Strength 22.7 Pin Threshold and Hysteresis 22.8 BOD Threshold 22.9 Internal Oscillator Speed 22.10 Current Consumption of Peripheral Units 22.11 Current Consumption in Reset and Reset Pulsewidth 23. Register Summary 24. Instruction Set Summary 25. Ordering Information 25.1 ATtiny25 25.2 ATtiny45 25.3 ATtiny85 26. Packaging Information 26.1 8P3 26.2 8S2 26.3 S8S1 26.4 8X 26.5 20M1 27. Errata 27.1 Errata ATtiny25 27.1.1 Rev D – F 27.1.2 Rev B – C 27.1.3 Rev A 27.2 Errata ATtiny45 27.2.1 Rev F – G 27.2.2 Rev D – E 27.2.3 Rev B – C 27.2.4 Rev A 27.3 Errata ATtiny85 27.3.1 Rev B – C 27.3.2 Rev A 28. Datasheet Revision History 28.1 Rev. 2586Q-08/13 28.2 Rev. 2586P-06/13 28.3 Rev. 2586O-02/13 28.4 Rev. 2586N-04/11 28.5 Rev. 2586M-07/10 28.6 Rev. 2586L-06/10 28.7 Rev. 2586K-01/08 28.8 Rev. 2586J-12/06 28.9 Rev. 2586I-09/06 28.10 Rev. 2586H-06/06 28.11 Rev. 2586G-05/06 28.12 Rev. 2586F-04/06 28.13 Rev. 2586E-03/06 28.14 Rev. 2586D-02/06 28.15 Rev. 2586C-06/05 28.16 Rev. 2586B-05/05 28.17 Rev. 2586A-02/05 Table of Contents