Datasheet ATtiny11, ATtiny12 - Summary (Atmel) - 5

ATtiny11/12 Pin Descriptions VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below.
Table 2.
PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option PB5 PB4 PB3
External Reset Enabled Used(1) -(2) - External Reset Disabled Input(3)/I/O(4) - - External Crystal - Used Used External Low-frequency Crystal - Used Used External Ceramic Resonator - Used Used External RC Oscillator - I/O(5) Used External Clock - I/O Used Internal RC Oscillator - I/O I/O Notes: 1. “Used” means the pin is used for reset or clock purposes. 2. “-” means the pin function is unaffected by the option. 3. Input means the pin is a port input pin. 4. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. 5. I/O means the pin is a port input/output pin.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
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1006FS–AVR–06/07 Document Outline Features Pin Configuration Overview ATtiny11 Block Diagram ATtiny12 Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET Register Summary ATtiny11 Register Summary ATtiny12 Instruction Set Summary Ordering Information ATtiny11 ATtiny12 Packaging Information 8P3 8S2 Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01