Datasheet AT90S2333, AT90LS2333, AT90S4433, AT90LS4433 - Preliminary (Atmel) - 6

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D- converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instruc- tions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec- tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe- cuted). The 8-bit stack pointer SP is read/write accessible in the I/O space. The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 3.
AT90S2333/4433 Memory Maps
Program Memory Data Memory
$000 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (1K/2K x 16) $005F $0060 Internal SRAM (128 x 8) $00DF $3FF/ $7FF A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro- gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
6 AT90S/LS2333 and AT90S/LS4433
Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations