Datasheet AT90S4434, AT90LS4434, AT90S8535, AT90LS8535 - Preliminary (Atmel) - 7

AT90S/LS4434 and AT90S/LS8535
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D- converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory. With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec- tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe- cuted). The 9/10-bit stack pointer SP is read/write accessible in the I/O space. The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 5.
Memory Maps
Program Memory Data Memory Data Memory
$000 32 Gen. Purpose $0000 $000 Working Registers $001F $0020 64 I/O Registers EEPROM Program Flash (256/512 x 8) (2K/4K x 16) $005F $0060 $0FF/$1FF Internal SRAM (256/512 x 8) $015F/$025F $7FF/$FFF A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro- gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
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Document Outline Features Description Block Diagram Comparison between AT90S4434 and AT90S8535 Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General Purpose Register File X-register, Y-register And Z-register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd And Rr I/O Direct Data Direct Data Indirect With Displacement Data Indirect Data Indirect With Pre-Decrement Data Indirect With Post-Increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP Reset and Interrupt Handling Reset Sources Power-On Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR External Interrupts Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Power Save Mode Timer / Counters Timer/Counter Prescalers 8-bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register - ICR1H AND ICR1L Timer/Counter1 In PWM Mode 8-bit Timer/Counter 2 Timer/Counter2 Control Register - TCCR2 Timer/Counter2 - TCNT2 Timer/Counter2 Output Compare Register - OCR2 Timer/Counter 2 in PWM mode Asynchronous Status Register - ASSR Asynchronous Operation of Timer/Counter2 Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH and EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR Baud Rate Generator UART Baud Rate Register - UBRR Analog Comparator Analog Comparator Control And Status Register - ACSR Analog to Digital Converter Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register - ADMUX ADC Control and Status Register - ADCSR ADC Data Register - ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics I/O-Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB Port B As General Digital I/O Alternate Functions Of Port B Port B Schematics Port C Port C Data Register - PORTC Port C Data Direction Register - DDRC Port C Input Pins Address - PINC Port C As General Digital I/O Alternate Functions of Port C Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Port D As General Digital I/O Alternate Functions Of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations