Datasheet AT90S4414, AT90S8515 (Atmel) - 6

The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system programmable Flash memory. With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space. The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 4.
The AT90S4414/8515 AVR RISC Architecture Data Bus 8-bit Program Status 2K/4K X 16 Control Counter and Test Program Registers Memory 32 x 8 Interrupt General Unit Instruction Purpose Register Registers SPI Unit Instruction Decoder Serial Uart ALU Control Lines 8-bit Timer/Counter Direct Addressing Indirect Addressing 16-bit Timer/Counter 256/512 x 8 with PWM Data SRAM Watchdog Timer 256/512 x 8 Analog EEPROM Comparator 32 I/O Lines
6 AT90S4414/8515
Document Outline Features Description Block Diagram Comparison Between AT90S4414 and AT90S8515 Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 ICP OC1B ALE Crystal Oscillator Architectural Overview General Purpose Register File X-Register, Y-Register And Z-Register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory - Internal and External Program and Data Addressing Modes Register Direct, Single Register RD Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre-decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR External Interrupts Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register - ICR1H AND ICR1L Timer/Counter1 In PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH and EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR BAUD Rate Generator UART BAUD Rate Register - UBRR Analog Comparator Analog Comparator Control And Status Register - ACSR Interface to External SRAM I/O-Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB PortB as General Digital I/O Alternate Functions of PortB Port B Schematics Port C Port C Data Register - PORTC Port C Data Direction Register - DDRC Port C Input Pins Address - PINC PortC as General Digital I/O Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND PortD as General Digital I/O Alternate Functions Of Port D PortD Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Data Memory Timing Typical Characteristics Instruction Set Summary (Continued) Ordering Information