Datasheet AT90S8515 (Atmel) - 3
| Fabricante | Atmel |
| Descripción | 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash |
| Páginas / Página | 112 / 3 — AT90S8515. Description The AT90S8515 is a low-power CMOS 8-bit … |
| Formato / tamaño de archivo | PDF / 2.7 Mb |
| Idioma del documento | Inglés |
AT90S8515. Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
Línea de modelo para esta hoja de datos
- AT90S8515-4AC AT90S8515-4AI AT90S8515-4JC AT90S8515-4JI AT90S8515-4PC AT90S8515-4PI AT90S8515-8AC AT90S8515-8AI AT90S8515-8JC AT90S8515-8JI AT90S8515-8PC AT90S8515-8PI AT90S8515A-4AC AT90S8515A-4AI AT90S8515A-4JC AT90S8515A-4JI AT90S8515A-4PC AT90S8515A-4PI AT90S8515A-8AC AT90S8515A-8AI AT90S8515A-8JC AT90S8515A-8JI AT90S8515A-8PC AT90S8515A-8PI
Versión de texto del documento
AT90S8515
Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8515
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed. Block Diagram Figure 1. The AT90S8515 Block Diagram The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in 3
0841G–09/01
Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8515
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed. Block Diagram Figure 1. The AT90S8515 Block Diagram The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in 3
0841G–09/01