Datasheet ATmega329/V, ATmega3290/V, ATmega649/V, ATmega6490/V - Complete (Atmel) - 10

6. AVR CPU Core 6.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
6.2 Architectural Overview Figure 6-1.
Block Diagram of the AVR Architecture Data Bus 8-bit Program Status Flash Counter and Control Program Memory Interrupt 32 x 8 Unit Instruction General Register Purpose SPI Registrers Unit Instruction Watchdog Decoder Timer ALU Analog Control Lines Comparator Direct Addressing Indirect Addressing I/O Module1 Data I/O Module 2 SRAM I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
10 ATmega329/3290/649/6490
2552K–AVR–04/11 Document Outline Features 1. Pin Configurations 2. Overview 2.1 Block Diagram 2.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 2.3 Pin Descriptions 2.3.1 VCC 2.3.2 GND 2.3.3 Port A (PA7..PA0) 2.3.4 Port B (PB7..PB0) 2.3.5 Port C (PC7..PC0) 2.3.6 Port D (PD7..PD0) 2.3.7 Port E (PE7..PE0) 2.3.8 Port F (PF7..PF0) 2.3.9 Port G (PG5..PG0) 2.3.10 Port H (PH7..PH0) 2.3.11 Port J (PJ6..PJ0) 2.3.12 RESET 2.3.13 XTAL1 2.3.14 XTAL2 2.3.15 AVCC 2.3.16 AREF 2.3.17 LCDCAP 3. Resources 4. Data Retention 5. About Code Examples 6. AVR CPU Core 6.1 Overview 6.2 Architectural Overview 6.3 ALU – Arithmetic Logic Unit 6.4 AVR Status Register 6.4.1 SREG – AVR Status Register 6.5 General Purpose Register File 6.5.1 The X-register, Y-register, and Z-register 6.6 Stack Pointer 6.7 Instruction Execution Timing 6.8 Reset and Interrupt Handling 6.8.1 Interrupt Response Time 7. AVR ATmega329/3290/649/6490 Memories 7.1 In-System Reprogrammable Flash Program Memory 7.2 SRAM Data Memory 7.2.1 Data Memory Access Times 7.3 EEPROM Data Memory 7.3.1 EEPROM Read/Write Access 7.3.2 EEPROM Write During Power-down Sleep Mode 7.3.3 Preventing EEPROM Corruption 7.4 I/O Memory 7.4.1 General Purpose I/O Registers 7.5 Register Description 7.5.1 EEARH and EEARL – The EEPROM Address Register 7.5.2 EEDR – The EEPROM Data Register 7.5.3 EECR – The EEPROM Control Register 7.5.4 GPIOR2 – General Purpose I/O Register 2 7.5.5 GPIOR1 – General Purpose I/O Register 1 7.5.6 GPIOR0 – General Purpose I/O Register 0 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution 8.1.1 CPU Clock – clkCPU 8.1.2 I/O Clock – clkI/O 8.1.3 Flash Clock – clkFLASH 8.1.4 Asynchronous Timer Clock – clkASY ADC Clock – clkADC 8.2 Clock Sources 8.2.1 Default Clock Source 8.3 Crystal Oscillator 8.4 Low-frequency Crystal Oscillator 8.5 Calibrated Internal RC Oscillator 8.6 External Clock 8.7 Clock Output Buffer 8.8 Timer/Counter Oscillator 8.9 System Clock Prescaler 8.9.1 Switching Time 8.10 Register Description 8.10.1 OSCCAL – Oscillator Calibration Register 8.10.2 CLKPR – Clock Prescale Register 9. Power Management and Sleep Modes 9.1 Idle Mode 9.2 ADC Noise Reduction Mode 9.3 Power-down Mode 9.4 Power-save Mode 9.5 Standby Mode 9.6 Power Reduction Register 9.7 Minimizing Power Consumption 9.7.1 Analog to Digital Converter 9.7.2 Analog Comparator 9.7.3 Brown-out Detector 9.7.4 Internal Voltage Reference 9.7.5 Watchdog Timer 9.7.6 Port Pins 9.7.7 JTAG Interface and On-chip Debug System 9.8 Register Description 9.8.1 SMCR – Sleep Mode Control Register 9.8.2 PRR – Power Reduction Register 10. System Control and Reset 10.1 Resetting the AVR 10.2 Reset Sources 10.3 Power-on Reset 10.4 External Reset 10.5 Brown-out Detection 10.6 Watchdog Reset 10.7 Internal Voltage Reference 10.7.1 Voltage Reference Enable Signals and Start-up Time 10.8 Watchdog Timer 10.9 Timed Sequences for Changing the Configuration of the Watchdog Timer 10.9.1 Safety Level 1 10.9.2 Safety Level 2 10.10 Register Description 10.10.1 MCUSR – MCU Status Register 10.10.2 WDTCR – Watchdog Timer Control Register 11. Interrupts 11.1 Interrupt Vectors in ATmega329/3290/649/6490 11.1.1 Moving Interrupts Between Application and Boot Space 11.2 Register Description 11.2.1 MCUCR – MCU Control Register 12. External Interrupts 12.1 Pin Change Interrupt Timing 12.2 Register Description 12.2.1 EICRA – External Interrupt Control Register A 12.2.2 External Interrupt Mask Register – EIMSK 12.2.3 EIFR – External Interrupt Flag Register 12.2.4 PCMSK3 – Pin Change Mask Register 3(1) 12.2.5 PCMSK2 – Pin Change Mask Register 2(1) 12.2.6 PCMSK1 – Pin Change Mask Register 1 12.2.7 PCMSK0 – Pin Change Mask Register 0 13. I/O-Ports 13.1 Introduction 13.2 Ports as General Digital I/O 13.2.1 Configuring the Pin 13.2.2 Toggling the Pin 13.2.3 Switching Between Input and Output 13.2.4 Reading the Pin Value 13.2.5 Digital Input Enable and Sleep Modes 13.2.6 Unconnected Pins 13.3 Alternate Port Functions 13.3.1 Alternate Functions of Port A 13.3.2 Alternate Functions of Port B 13.3.3 Alternate Functions of Port C 13.3.4 Alternate Functions of Port D 13.3.5 Alternate Functions of Port E 13.3.6 Alternate Functions of Port F 13.3.7 Alternate Functions of Port G 13.3.8 Alternate Functions of Port H 13.3.9 Alternate Functions of Port J 13.4 Register Description 13.4.1 MCUCR – MCU Control Register 13.4.2 PORTA – Port A Data Register 13.4.3 DDRA – Port A Data Direction Register 13.4.4 PINA – Port A Input Pins Address 13.4.5 PORTB – Port B Data Register 13.4.6 DDRB – Port B Data Direction Register 13.4.7 PINB – Port B Input Pins Address 13.4.8 PORTC – Port C Data Register 13.4.9 DDRC – Port C Data Direction Register 13.4.10 PINC – Port C Input Pins Address 13.4.11 PORTD – Port D Data Register 13.4.12 DDRD – Port D Data Direction Register 13.4.13 PIND – Port D Input Pins Address 13.4.14 PORTE – Port E Data Register 13.4.15 DDRE – Port E Data Direction Register 13.4.16 PINE – Port E Input Pins Address 13.4.17 PORTF – Port F Data Register 13.4.18 DDRF – Port F Data Direction Register 13.4.19 PINF – Port F Input Pins Address 13.4.20 PORTG – Port G Data Register 13.4.21 DDRG – Port G Data Direction Register 13.4.22 PING – Port G Input Pins Address 13.4.23 PORTH – Port H Data Register(1) 13.4.24 DDRH – Port H Data Direction Register(1) 13.4.25 PINH – Port H Input Pins Address(1) 13.4.26 PORTJ – Port J Data Register(1) 13.4.27 DDRJ – Port J Data Direction Register(1) 13.4.28 PINJ – Port J Input Pins Address(1) 14. 8-bit Timer/Counter0 with PWM 14.1 Features 14.2 Overview 14.2.1 Registers 14.2.2 Definitions 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Output Compare Unit 14.5.1 Force Output Compare 14.5.2 Compare Match Blocking by TCNT0 Write 14.5.3 Using the Output Compare Unit 14.6 Compare Match Output Unit 14.6.1 Compare Output Mode and Waveform Generation 14.7 Modes of Operation 14.7.1 Normal Mode 14.7.2 Clear Timer on Compare Match (CTC) Mode 14.7.3 Fast PWM Mode 14.7.4 Phase Correct PWM Mode 14.8 Timer/Counter Timing Diagrams 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A 14.9.2 TCNT0 – Timer/Counter Register 14.9.3 OCR0A – Output Compare Register A 14.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 14.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register 15. Timer/Counter0 and Timer/Counter1 Prescalers 15.0.1 Internal Clock Source 15.0.2 Prescaler Reset 15.0.3 External Clock Source 15.1 Register Description 15.1.1 GTCCR – General Timer/Counter Control Register 16. 16-bit Timer/Counter1 16.1 Features 16.2 Overview 16.2.1 Registers 16.2.2 Definitions 16.2.3 Compatibility 16.3 Accessing 16-bit Registers 16.3.1 Reusing the Temporary High Byte Register 16.4 Timer/Counter Clock Sources 16.5 Counter Unit 16.6 Input Capture Unit 16.6.1 Input Capture Trigger Source 16.6.2 Noise Canceler 16.6.3 Using the Input Capture Unit 16.7 Output Compare Units 16.7.1 Force Output Compare 16.7.2 Compare Match Blocking by TCNT1 Write 16.7.3 Using the Output Compare Unit 16.8 Compare Match Output Unit 16.8.1 Compare Output Mode and Waveform Generation 16.9 Modes of Operation 16.9.1 Normal Mode 16.9.2 Clear Timer on Compare Match (CTC) Mode 16.9.3 Fast PWM Mode 16.9.4 Phase Correct PWM Mode 16.9.5 Phase and Frequency Correct PWM Mode 16.10 Timer/Counter Timing Diagrams 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A 16.11.2 TCCR1B – Timer/Counter1 Control Register B 16.11.3 TCCR1C – Timer/Counter1 Control Register C 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 16.11.7 ICR1H and ICR1L – Input Capture Register 1 16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 17.1 Features 17.2 Overview 17.2.1 Registers 17.2.2 Definitions 17.3 Timer/Counter Clock Sources 17.4 Counter Unit 17.5 Output Compare Unit 17.5.1 Force Output Compare 17.5.2 Compare Match Blocking by TCNT2 Write 17.5.3 Using the Output Compare Unit 17.6 Compare Match Output Unit 17.6.1 Compare Output Mode and Waveform Generation 17.7 Modes of Operation 17.7.1 Normal Mode 17.7.2 Clear Timer on Compare Match (CTC) Mode 17.7.3 Fast PWM Mode 17.7.4 Phase Correct PWM Mode 17.8 Timer/Counter Timing Diagrams 17.9 Asynchronous Operation of Timer/Counter2 17.10 Timer/Counter Prescaler 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control Register A 17.11.2 TCNT2 – Timer/Counter Register 17.11.3 OCR2A – Output Compare Register A 17.11.4 ASSR – Asynchronous Status Register 17.11.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register 17.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register 17.11.7 GTCCR – General Timer/Counter Control Register 18. SPI – Serial Peripheral Interface 18.1 Features 18.2 Overview 18.3 SS Pin Functionality 18.3.1 Slave Mode 18.3.2 Master Mode 18.4 Data Modes 18.5 Register Description 18.5.1 SPCR – SPI Control Register 18.5.2 SPSR – SPI Status Register 18.5.3 SPDR – SPI Data Register 19. USART0 19.1 Features 19.2 Overview 19.2.1 AVR USART vs. AVR UART – Compatibility 19.3 Clock Generation 19.3.1 Internal Clock Generation – The Baud Rate Generator 19.3.2 Double Speed Operation (U2Xn) 19.3.3 External Clock 19.3.4 Synchronous Clock Operation 19.4 Frame Formats 19.4.1 Parity Bit Calculation 19.5 USART Initialization 19.6 Data Transmission – The USART Transmitter 19.6.1 Sending Frames with 5 to 8 Data Bit 19.6.2 Sending Frames with 9 Data Bit 19.6.3 Transmitter Flags and Interrupts 19.6.4 Parity Generator 19.6.5 Disabling the Transmitter 19.7 Data Reception – The USART Receiver 19.7.1 Receiving Frames with 5 to 8 Data Bits 19.7.2 Receiving Frames with 9 Data Bits 19.7.3 Receive Compete Flag and Interrupt 19.7.4 Receiver Error Flags 19.7.5 Parity Checker 19.7.6 Disabling the Receiver 19.7.7 Flushing the Receive Buffer 19.8 Asynchronous Data Reception 19.8.1 Asynchronous Clock Recovery 19.8.2 Asynchronous Data Recovery 19.8.3 Asynchronous Operational Range 19.9 Multi-processor Communication Mode 19.9.1 Using MPCM 19.10 Examples of Baud Rate Setting 19.11 Register Description 19.11.1 UDRn – USART I/O Data Register n 19.11.2 UCSRnA – USART Control and Status Register n A 19.11.3 UCSRnB – USART Control and Status Register n B 19.11.4 UCSRnC – USART Control and Status Register n C 19.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers n 20. USI – Universal Serial Interface 20.1 Features 20.2 Overview 20.3 Functional Descriptions 20.3.1 Three-wire Mode 20.3.2 SPI Master Operation Example 20.3.3 SPI Slave Operation Example 20.3.4 Two-wire Mode 20.3.5 Start Condition Detector 20.3.6 Clock speed considerations. 20.4 Alternative USI Usage 20.4.1 Half-duplex Asynchronous Data Transfer 20.4.2 4-bit Counter 20.4.3 12-bit Timer/Counter 20.4.4 Edge Triggered External Interrupt 20.4.5 Software Interrupt 20.5 Register Descriptions 20.5.1 USIDR – USI Data Register 20.5.2 USISR – USI Status Register 20.5.3 USICR – USI Control Register 21. Analog Comparator 21.1 Overview 21.2 Analog Comparator Multiplexed Input 21.3 Register Description 21.3.1 ADCSRB – ADC Control and Status Register B 21.3.2 ACSR – Analog Comparator Control and Status Register 21.3.3 DIDR1 – Digital Input Disable Register 1 22. Analog to Digital Converter 22.1 Features 22.2 Operation 22.3 Starting a Conversion 22.4 Prescaling and Conversion Timing 22.5 Changing Channel or Reference Selection 22.5.1 ADC Input Channels 22.5.2 ADC Voltage Reference 22.5.3 ADC Noise Canceler 22.5.4 Analog Input Circuitry 22.5.5 Analog Noise Canceling Techniques 22.5.6 ADC Accuracy Definitions 22.6 ADC Conversion Result 22.7 Register Description 22.7.1 ADMUX – ADC Multiplexer Selection Register 22.7.2 ADCSRA – ADC Control and Status Register A 22.7.3 ADCL and ADCH – The ADC Data Register 22.7.4 ADCSRB – ADC Control and Status Register B 22.7.5 DIDR0 – Digital Input Disable Register 0 23. LCD Controller 23.1 Features 23.1.1 Overview 23.1.2 Definitions 23.1.3 LCD Clock Sources 23.1.4 LCD Prescaler 23.1.5 LCD Memory 23.1.6 LCD Contrast Controller/Power Supply 23.1.7 LCDCAP 23.1.8 LCD Buffer Driver 23.1.9 Display requirements 23.1.10 Minimizing power consumption 23.2 Mode of Operation 23.2.1 Static Duty and Bias 23.2.2 1/2 Duty and 1/2 Bias 23.2.3 1/3 Duty and 1/3 Bias 23.2.4 1/4 Duty and 1/3 Bias 23.2.5 Low Power Waveform 23.2.6 Operation in Sleep Mode 23.2.7 Display Blanking 23.2.8 Port Mask 23.3 LCD Usage 23.3.1 LCD Initialization 23.3.2 Updating the LCD 23.3.3 Disabling the LCD 23.4 Register Description 23.4.1 LCDCRA – LCD Control and Status Register A 23.4.2 LCDCRB – LCD Control and Status Register B 23.4.3 LCDFRR – LCD Frame Rate Register 23.4.4 LCDCCR – LCD Contrast Control Register 23.4.5 LCD Memory Mapping 24. JTAG Interface and On-chip Debug System 24.1 Features 24.2 Overview 24.3 Test Access Port – TAP 24.4 TAP Controller 24.5 Using the Boundary-scan Chain 24.6 Using the On-chip Debug System 24.7 On-chip Debug Specific JTAG Instructions 24.7.1 PRIVATE0; 0x8 24.7.2 PRIVATE1; 0x9 24.7.3 PRIVATE2; 0xA 24.7.4 PRIVATE3; 0xB 24.8 Using the JTAG Programming Capabilities 24.9 Bibliography 24.10 Register Description 24.10.1 OCDR – On-chip Debug Register 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features 25.2 System Overview 25.3 Data Registers 25.3.1 Bypass Register 25.3.2 Device Identification Register 25.3.3 Reset Register 25.3.4 Boundary-scan Chain 25.4 Boundary-scan Specific JTAG Instructions 25.4.1 EXTEST; 0x0 25.4.2 IDCODE; 0x1 25.4.3 SAMPLE_PRELOAD; 0x2 25.4.4 AVR_RESET; 0xC 25.4.5 BYPASS; 0xF 25.5 Boundary-scan Related Register in I/O Memory 25.5.1 MCUCR – MCU Control Register 25.5.2 MCUSR – MCU Status Register 25.6 Boundary-scan Chain 25.6.1 Scanning the Digital Port Pins 25.6.2 Scanning the RESET Pin 25.6.3 Scanning the Clock Pins 25.6.4 Scanning the Analog Comparator 25.6.5 Scanning the ADC 25.7 ATmega329/3290/649/6490 Boundary-scan Order 25.8 Boundary-scan Description Language Files 26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features 26.2 Application and Boot Loader Flash Sections 26.2.1 Application Section 26.2.2 BLS – Boot Loader Section 26.3 Read-While-Write and No Read-While-Write Flash Sections 26.3.1 RWW – Read-While-Write Section 26.3.2 NRWW – No Read-While-Write Section 26.4 Boot Loader Lock Bits 26.5 Entering the Boot Loader Program 26.6 Addressing the Flash During Self-Programming 26.7 Self-Programming the Flash 26.7.1 Performing Page Erase by SPM 26.7.2 Filling the Temporary Buffer (Page Loading) 26.7.3 Performing a Page Write 26.7.4 Using the SPM Interrupt 26.7.5 Consideration While Updating BLS 26.7.6 Prevent Reading the RWW Section During Self-Programming 26.7.7 Setting the Boot Loader Lock Bits by SPM 26.7.8 EEPROM Write Prevents Writing to SPMCSR 26.7.9 Reading the Fuse and Lock Bits from Software 26.7.10 Preventing Flash Corruption 26.7.11 Programming Time for Flash when Using SPM 26.7.12 Simple Assembly Code Example for a Boot Loader 26.7.13 ATmega329/3290/649/6490 Boot Loader Parameters 26.8 Register Description 26.8.1 SPMCSR – Store Program Memory Control and Status Register 27. Memory Programming 27.1 Program And Data Memory Lock Bits 27.2 Fuse Bits 27.2.1 Latching of Fuses 27.3 Signature Bytes 27.4 Calibration Byte 27.5 Parallel Programming Parameters, Pin Mapping, and Commands 27.5.1 Signal Names 27.6 Parallel Programming 27.6.1 Enter Programming Mode 27.6.2 Considerations for Efficient Programming 27.6.3 Chip Erase 27.6.4 Programming the Flash 27.6.5 Programming the EEPROM 27.6.6 Reading the Flash 27.6.7 Reading the EEPROM 27.6.8 Programming the Fuse Low Bits 27.6.9 Programming the Fuse High Bits 27.6.10 Programming the Extended Fuse Bits 27.6.11 Programming the Lock Bits 27.6.12 Reading the Fuse and Lock Bits 27.6.13 Reading the Signature Bytes 27.6.14 Reading the Calibration Byte 27.6.15 Parallel Programming Characteristics 27.7 Serial Downloading 27.7.1 Serial Programming Pin Mapping 27.7.2 Serial Programming Algorithm 27.7.3 Serial Programming Instruction set 27.7.4 SPI Serial Programming Characteristics 27.8 Programming via the JTAG Interface 27.8.1 Programming Specific JTAG Instructions 27.8.2 AVR_RESET (0xC) 27.8.3 PROG_ENABLE (0x4) 27.8.4 PROG_COMMANDS (0x5) 27.8.5 PROG_PAGELOAD (0x6) 27.8.6 PROG_PAGEREAD (0x7) 27.8.7 Data Registers 27.8.8 Reset Register 27.8.9 Programming Enable Register 27.8.10 Programming Command Register 27.8.11 Flash Data Byte Register 27.8.12 Programming Algorithm 27.8.13 Entering Programming Mode 27.8.14 Leaving Programming Mode 27.8.15 Performing Chip Erase 27.8.16 Programming the Flash 27.8.17 Reading the Flash 27.8.18 Programming the EEPROM 27.8.19 Reading the EEPROM 27.8.20 Programming the Fuses 27.8.21 Programming the Lock Bits Reading the Fuses and Lock Bits Reading the Signature Bytes Reading the Calibration Byte 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* 28.2 DC Characteristics 28.3 Speed Grades 28.4 Clock Characteristics 28.4.1 Calibrated Internal RC Oscillator Accuracy 28.4.2 External Clock Drive Waveforms 28.4.3 External Clock Drive 28.5 System and Reset Characteristics 28.6 SPI Timing Characteristics 28.7 ADC Characteristics 28.8 LCD Controller Characteristics 29. Typical Characteristics 29.0.1 Active Supply Current 29.0.2 Idle Supply Current 29.0.3 Supply Current of I/O modules 29.0.4 Power-down Supply Current 29.0.5 Power-save Supply Current 29.0.6 Standby Supply Current 29.0.7 Pin Pull-up 29.0.8 Pin Driver Strength 29.0.9 Pin Thresholds and hysteresis 29.0.10 BOD Thresholds and Analog Comparator Offset 29.0.11 Internal Oscillator Speed 29.0.12 Current Consumption of Peripheral Units 29.0.13 Current Consumption in Reset and Reset Pulsewidth 30. Register Summary 31. Instruction Set Summary 32. Ordering Information 32.1 ATmega329 32.2 ATmega3290 32.3 ATmega649 32.4 ATmega6490 33. Packaging Information 33.1 64A 33.2 64M1 33.3 100A 34. Errata 34.1 ATmega329 34.1.1 ATmega329 rev. C 34.1.2 ATmega329 rev. B 34.1.3 ATmega329 rev. A 34.2 ATmega3290 34.2.1 ATmega3290 rev. C 34.2.2 ATmega3290 rev. B 34.2.3 ATmega3290 rev. A 34.3 ATmega649 34.3.1 ATmega649 rev. A 34.4 ATmega6490 34.4.1 ATmega6490 rev. A 35. Datasheet Revision History 35.1 Rev. 2552K – 04/11 35.2 Rev. 2552J – 08/07 35.3 Rev. 2552I – 04/07 35.4 Rev. 2552H – 11/06 35.5 Rev. 2552G – 07/06 35.6 Rev. 2552F – 06/06 35.7 Rev. 2552E – 04/06 35.8 Rev. 2552D – 03/06 35.9 Rev. 2552C – 03/06 35.10 Rev. 2552B – 05/05 35.11 Rev. 2552A –11/04 Table of Contents