Datasheet ATmega325P/V, ATmega3250P/V - Preliminary (Atmel)

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Features
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High Performance, Low Power AVR
®
8-Bit Microcontroller
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Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-Chip 2-cycle Multiplier
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High Endurance Non-volatile Memory segments – 32K Bytes of In-System Self-programmable Flash program memory – 1K Bytes EEPROM – 2K Bytes Internal SRAM 8-bit – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C
(1)
– Optional Boot Code Section with Independent Lock Bits Microcontroller In-System Programming by On-chip Boot Program True Read-While-Write Operation with 32K Bytes – Programming Lock for Software Security
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JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard In-System – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Programmable
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Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode Flash – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC ATmega325P/V – Programmable Serial USART – Master/Slave SPI Serial Interface ATmega3250P/V – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change
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Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator Preliminary – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
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I/O and Packages – 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
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Speed Grade: – ATmega325PV/ATmega3250PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATmega325P/3250P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
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Temperature range: – -40°C to 85°C Industrial
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Ultra-Low Power Consumption – Active Mode: 420 µA at 1 MHz, 1.8V – Power-down Mode: 40 nA at 1.8V – Power-save Mode: 750 nA at 1.8V
8023F–AVR–07/09 Document Outline Features 1. Pin Configurations 1.1 Disclaimer 2. Overview 2.1 Block Diagram 2.2 Comparison between ATmega325P and ATmega3250P 2.3 Pin Descriptions 2.3.1 VCC 2.3.2 GND 2.3.3 Port A (PA7..PA0) 2.3.4 Port B (PB7..PB0) 2.3.5 Port C (PC7..PC0) 2.3.6 Port D (PD7..PD0) 2.3.7 Port E (PE7..PE0) 2.3.8 Port F (PF7..PF0) 2.3.9 Port G (PG5..PG0) 2.3.10 Port H (PH7..PH0) 2.3.11 Port J (PJ6..PJ0) 2.3.12 RESET 2.3.13 XTAL1 2.3.14 XTAL2 2.3.15 AVCC 2.3.16 AREF 3. Resources 4. Data Retention 5. About Code Examples 6. AVR CPU Core 6.1 Overview 6.2 Architectural Overview 6.3 ALU – Arithmetic Logic Unit 6.4 AVR Status Register 6.4.1 SREG – AVR Status Register 6.5 General Purpose Register File 6.5.1 The X-register, Y-register, and Z-register 6.6 Stack Pointer 6.6.1 SPH and SPL – Stack Pointer High and Stack Pointer Low 6.7 Instruction Execution Timing 6.8 Reset and Interrupt Handling 6.8.1 Interrupt Response Time 7. AVR Memories 7.1 Overview 7.2 In-System Reprogrammable Flash Program Memory 7.3 SRAM Data Memory 7.3.1 Data Memory Access Times 7.4 EEPROM Data Memory 7.4.1 EEPROM Read/Write Access 7.4.2 EEPROM Write During Power-down Sleep Mode 7.4.3 Preventing EEPROM Corruption 7.5 I/O Memory 7.6 Register Description 7.6.1 EEARH and EEARL – The EEPROM Address Register 7.6.2 EEDR – The EEPROM Data Register 7.6.3 EECR – The EEPROM Control Register 7.6.4 General Purpose I/O Registers 7.6.5 GPIOR2 – General Purpose I/O Register 2 7.6.6 GPIOR1 – General Purpose I/O Register 1 7.6.7 GPIOR0 – General Purpose I/O Register 0 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution 8.1.1 CPU Clock – clkCPU 8.1.2 I/O Clock – clkI/O 8.1.3 Flash Clock – clkFLASH 8.1.4 Asynchronous Timer Clock – clkASY 8.1.5 ADC Clock – clkADC 8.2 Clock Sources 8.3 Default Clock Source 8.4 Crystal Oscillator 8.5 Low-frequency Crystal Oscillator 8.6 Calibrated Internal RC Oscillator 8.7 External Clock 8.8 Clock Output Buffer 8.9 Timer/Counter Oscillator 8.10 System Clock Prescaler 8.10.1 Switching Time 8.11 Register Description 8.11.1 OSCCAL – Oscillator Calibration Register 8.11.2 CLKPR – Clock Prescale Register 9. Power Management and Sleep Modes 9.1 Overview 9.2 Sleep Modes 9.3 BOD Disable 9.4 Idle Mode 9.5 ADC Noise Reduction Mode 9.6 Power-down Mode 9.7 Power-save Mode 9.8 Standby Mode 9.9 Power Reduction Register 9.10 Minimizing Power Consumption 9.10.1 Analog to Digital Converter 9.10.2 Analog Comparator 9.10.3 Brown-out Detector 9.10.4 Internal Voltage Reference 9.10.5 Watchdog Timer 9.10.6 Port Pins 9.10.7 JTAG Interface and On-chip Debug System 9.11 Register Description 9.11.1 SMCR – Sleep Mode Control Register 9.11.2 MCUCR – MCU Control Register 9.11.3 PRR – Power Reduction Register 10. System Control and Reset 10.1 Resetting the AVR 10.2 Reset Sources 10.2.1 Power-on Reset 10.2.2 External Reset 10.2.3 Brown-out Detection 10.2.4 Watchdog Reset 10.3 Internal Voltage Reference 10.3.1 Voltage Reference Enable Signals and Start-up Time 10.4 Watchdog Timer 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer 10.4.2 Safety Level 1 10.4.3 Safety Level 2 10.5 Register Description 10.5.1 MCUSR – MCU Status Register 10.5.2 WDTCR – Watchdog Timer Control Register 11. Interrupts 11.1 Overview 11.2 Interrupt Vectors 11.2.1 Moving Interrupts Between Application and Boot Space 11.3 Register Description 11.3.1 MCUCR – MCU Control Register 12. External Interrupts 12.1 Overview 12.2 Pin Change Interrupt Timing 12.3 Register Description 12.3.1 EICRA – External Interrupt Control Register A 12.3.2 EIMSK – External Interrupt Mask Register 12.3.3 EIFR – External Interrupt Flag Register 12.3.4 PCMSK3 – Pin Change Mask Register 3(1) 12.3.5 PCMSK2 – Pin Change Mask Register 2(1) 12.3.6 PCMSK1 – Pin Change Mask Register 1 12.3.7 PCMSK0 – Pin Change Mask Register 0 13. I/O-Ports 13.1 Overview 13.2 Ports as General Digital I/O 13.2.1 Configuring the Pin 13.2.2 Toggling the Pin 13.2.3 Switching Between Input and Output 13.2.4 Reading the Pin Value 13.2.5 Digital Input Enable and Sleep Modes 13.2.6 Unconnected Pins 13.3 Alternate Port Functions 13.3.1 Alternate Functions of Port B 13.3.2 Alternate Functions of Port D 13.3.3 Alternate Functions of Port E 13.3.4 Alternate Functions of Port F 13.3.5 Alternate Functions of Port G 13.3.6 Alternate Functions of Port H 13.3.7 Alternate Functions of Port J 13.4 Register Description 13.4.1 MCUCR – MCU Control Register 13.4.2 PORTA – Port A Data Register 13.4.3 DDRA – Port A Data Direction Register 13.4.4 PINA – Port A Input Pins Address 13.4.5 PORTB – Port B Data Register 13.4.6 DDRB – Port B Data Direction Register 13.4.7 PINB – Port B Input Pins Address 13.4.8 PORTC – Port C Data Register 13.4.9 DDRC – Port C Data Direction Register 13.4.10 PINC – Port C Input Pins Address 13.4.11 PORTD – Port D Data Register 13.4.12 DDRD – Port D Data Direction Register 13.4.13 PIND – Port D Input Pins Address 13.4.14 PORTE – Port E Data Register 13.4.15 DDRE – Port E Data Direction Register 13.4.16 PINE – Port E Input Pins Address 13.4.17 PORTF – Port F Data Register 13.4.18 DDRF – Port F Data Direction Register 13.4.19 PINF – Port F Input Pins Address 13.4.20 PORTG – Port G Data Register 13.4.21 DDRG – Port G Data Direction Register 13.4.22 PING – Port G Input Pins Address 13.4.23 PORTH – Port H Data Register(1) 13.4.24 DDRH – Port H Data Direction Register(1) 13.4.25 PINH – Port H Input Pins Address(1) 13.4.26 PORTJ – Port J Data Register(1) 13.4.27 DDRJ – Port J Data Direction Register(1) 13.4.28 PINJ – Port J Input Pins Address(1) 14. 8-bit Timer/Counter0 with PWM 14.1 Features 14.2 Overview 14.2.1 Registers 14.2.2 Definitions 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Output Compare Unit 14.5.1 Force Output Compare 14.5.2 Compare Match Blocking by TCNT0 Write 14.5.3 Using the Output Compare Unit 14.6 Compare Match Output Unit 14.6.1 Compare Output Mode and Waveform Generation 14.7 Modes of Operation 14.7.1 Normal Mode 14.7.2 Clear Timer on Compare Match (CTC) Mode 14.7.3 Fast PWM Mode 14.7.4 Phase Correct PWM Mode 14.8 Timer/Counter Timing Diagrams 14.9 Timer/Counter0 and Timer/Counter1 Prescalers 14.9.1 Internal Clock Source 14.9.2 Prescaler Reset 14.9.3 External Clock Source 14.10 Register Description 14.10.1 TCCR0A – Timer/Counter Control Register A 14.10.2 TCNT0 – Timer/Counter Register 14.10.3 OCR0A – Output Compare Register A 14.10.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 14.10.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register 14.10.6 GTCCR – General Timer/Counter Control Register 15. 16-bit Timer/Counter1 15.1 Features 15.2 Overview 15.2.1 Registers 15.2.2 Definitions 15.2.3 Compatibility 15.3 Accessing 16-bit Registers 15.3.1 Reusing the Temporary High Byte Register 15.4 Timer/Counter Clock Sources 15.5 Counter Unit 15.6 Input Capture Unit 15.6.1 Input Capture Trigger Source 15.6.2 Noise Canceler 15.6.3 Using the Input Capture Unit 15.7 Output Compare Units 15.7.1 Force Output Compare 15.7.2 Compare Match Blocking by TCNT1 Write 15.7.3 Using the Output Compare Unit 15.8 Compare Match Output Unit 15.8.1 Compare Output Mode and Waveform Generation 15.9 Modes of Operation 15.9.1 Normal Mode 15.9.2 Clear Timer on Compare Match (CTC) Mode 15.9.3 Fast PWM Mode 15.9.4 Phase Correct PWM Mode 15.9.5 Phase and Frequency Correct PWM Mode 15.10 Timer/Counter Timing Diagrams 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A 15.11.2 TCCR1B – Timer/Counter1 Control Register B 15.11.3 TCCR1C – Timer/Counter1 Control Register C 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 15.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 15.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 15.11.7 ICR1H and ICR1L – Input Capture Register 1 15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 16. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 16.1 Features 16.2 Overview 16.2.1 Registers 16.2.2 Definitions 16.3 Timer/Counter Clock Sources 16.4 Counter Unit 16.5 Output Compare Unit 16.5.1 Force Output Compare 16.5.2 Compare Match Blocking by TCNT2 Write 16.5.3 Using the Output Compare Unit 16.6 Compare Match Output Unit 16.6.1 Compare Output Mode and Waveform Generation 16.7 Modes of Operation 16.7.1 Normal Mode 16.7.2 Clear Timer on Compare Match (CTC) Mode 16.7.3 Fast PWM Mode 16.7.4 Phase Correct PWM Mode 16.8 Timer/Counter Timing Diagrams 16.9 Asynchronous Operation of Timer/Counter2 16.9.1 Timer/Counter Prescaler 16.10 Register Description 16.10.1 TCCR2A – Timer/Counter Control Register A 16.10.2 TCNT2 – Timer/Counter Register 16.10.3 OCR2A – Output Compare Register A 16.10.4 ASSR – Asynchronous Status Register 16.10.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register 16.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register 16.10.7 GTCCR – General Timer/Counter Control Register 17. SPI – Serial Peripheral Interface 17.1 Features 17.2 Overview 17.3 SS Pin Functionality 17.3.1 Slave Mode 17.3.2 Master Mode 17.4 Data Modes 17.5 Register Description 17.5.1 SPCR – SPI Control Register 17.5.2 SPSR – SPI Status Register 17.5.3 SPDR – SPI Data Register 18. USART0 18.1 Features 18.2 Overview 18.2.1 AVR USART vs. AVR UART – Compatibility 18.3 Clock Generation 18.3.1 Internal Clock Generation – The Baud Rate Generator 18.3.2 Double Speed Operation (U2Xn) 18.3.3 External Clock 18.3.4 Synchronous Clock Operation 18.4 Frame Formats 18.4.1 Parity Bit Calculation 18.5 USART Initialization 18.6 Data Transmission – The USART Transmitter 18.6.1 Sending Frames with 5 to 8 Data Bit 18.6.2 Sending Frames with 9 Data Bit 18.6.3 Transmitter Flags and Interrupts 18.6.4 Parity Generator 18.6.5 Disabling the Transmitter 18.7 Data Reception – The USART Receiver 18.7.1 Receiving Frames with 5 to 8 Data Bits 18.7.2 Receiving Frames with 9 Data Bits 18.7.3 Receive Compete Flag and Interrupt 18.7.4 Receiver Error Flags 18.7.5 Parity Checker 18.7.6 Disabling the Receiver 18.7.7 Flushing the Receive Buffer 18.8 Asynchronous Data Reception 18.8.1 Asynchronous Clock Recovery 18.8.2 Asynchronous Data Recovery 18.8.3 Asynchronous Operational Range 18.9 Multi-processor Communication Mode 18.9.1 Using MPCM 18.10 Register Description 18.10.1 UDRn – USART I/O Data Register n 18.10.2 UCSRnA – USART Control and Status Register n A 18.10.3 UCSRnB – USART Control and Status Register n B 18.10.4 UCSRnC – USART Control and Status Register n C 18.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers n 18.11 Examples of Baud Rate Setting 19. USI – Universal Serial Interface 19.1 Features 19.2 Overview 19.3 Functional Descriptions 19.3.1 Three-wire Mode 19.3.2 SPI Master Operation Example 19.3.3 SPI Slave Operation Example 19.3.4 Two-wire Mode 19.3.5 Start Condition Detector 19.3.6 Clock speed considerations. 19.4 Alternative USI Usage 19.4.1 Half-duplex Asynchronous Data Transfer 19.4.2 4-bit Counter 19.4.3 12-bit Timer/Counter 19.4.4 Edge Triggered External Interrupt 19.4.5 Software Interrupt 19.5 Register Descriptions 19.5.1 USIDR – USI Data Register 19.5.2 USISR – USI Status Register 19.5.3 USICR – USI Control Register 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Multiplexed Input 20.3 Register Description 20.3.1 ADCSRB – ADC Control and Status Register B 20.3.2 ACSR – Analog Comparator Control and Status Register 20.3.3 DIDR1 – Digital Input Disable Register 1 21. Analog to Digital Converter 21.1 Features 21.2 Overview 21.3 Operation 21.4 Starting a Conversion 21.5 Prescaling and Conversion Timing 21.6 Changing Channel or Reference Selection 21.6.1 ADC Input Channels 21.6.2 ADC Voltage Reference 21.7 ADC Noise Canceler 21.7.1 Analog Input Circuitry 21.7.2 Analog Noise Canceling Techniques 21.7.3 ADC Accuracy Definitions 21.8 ADC Conversion Result 21.9 Register Description 21.9.1 ADMUX – ADC Multiplexer Selection Register 21.9.2 ADCSRA – ADC Control and Status Register A 21.9.3 ADCL and ADCH – The ADC Data Register 21.9.4 ADCSRB – ADC Control and Status Register B 21.9.5 DIDR0 – Digital Input Disable Register 0 22. JTAG Interface and On-chip Debug System 22.1 Features 22.2 Overview 22.3 TAP – Test Access Port 22.4 TAP Controller 22.5 Using the Boundary-scan Chain 22.6 Using the On-chip Debug System 22.7 On-chip Debug Specific JTAG Instructions 22.7.1 PRIVATE0; 0x8 22.7.2 PRIVATE1; 0x9 22.7.3 PRIVATE2; 0xA 22.7.4 PRIVATE3; 0xB 22.8 Using the JTAG Programming Capabilities 22.9 Bibliography 22.10 Register Description 22.10.1 OCDR – On-chip Debug Register 23. IEEE 1149.1 (JTAG) Boundary-scan 23.1 Features 23.2 Overview 23.3 Data Registers 23.3.1 Bypass Register 23.3.2 Device Identification Register 23.3.3 Reset Register 23.3.4 Boundary-scan Chain 23.4 Boundary-scan Specific JTAG Instructions 23.4.1 EXTEST; 0x0 23.4.2 IDCODE; 0x1 23.4.3 SAMPLE_PRELOAD; 0x2 23.4.4 AVR_RESET; 0xC 23.4.5 BYPASS; 0xF 23.5 Boundary-scan Chain 23.5.1 Scanning the Digital Port Pins 23.5.2 Scanning the RESET Pin 23.5.3 Scanning the Clock Pins 23.5.4 Scanning the Analog Comparator 23.5.5 Scanning the ADC 23.6 ATmega325P/3250P Boundary-scan Order 23.7 Boundary-scan Description Language Files 23.8 Register Description 23.8.1 MCUCR – MCU Control Register 23.8.2 MCUSR – MCU Status Register 24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Features 24.2 Overview 24.3 Application and Boot Loader Flash Sections 24.3.1 Application Section 24.3.2 BLS – Boot Loader Section 24.4 Read-While-Write and No Read-While-Write Flash Sections 24.4.1 RWW – Read-While-Write Section 24.4.2 NRWW – No Read-While-Write Section 24.5 Boot Loader Lock Bits 24.6 Entering the Boot Loader Program 24.7 Addressing the Flash During Self-Programming 24.8 Self-Programming the Flash 24.8.1 Performing Page Erase by SPM 24.8.2 Filling the Temporary Buffer (Page Loading) 24.8.3 Performing a Page Write 24.8.4 Using the SPM Interrupt 24.8.5 Consideration While Updating BLS 24.8.6 Prevent Reading the RWW Section During Self-Programming 24.8.7 Setting the Boot Loader Lock Bits by SPM 24.8.8 EEPROM Write Prevents Writing to SPMCSR 24.8.9 Reading the Fuse and Lock Bits from Software 24.8.10 Preventing Flash Corruption 24.8.11 Programming Time for Flash when Using SPM 24.8.12 Simple Assembly Code Example for a Boot Loader 24.8.13 ATmega325P/3250P Boot Loader Parameters 24.9 Register Description 24.9.1 SPMCSR – Store Program Memory Control and Status Register 25. Memory Programming 25.1 Program And Data Memory Lock Bits 25.2 Fuse Bits 25.2.1 Latching of Fuses 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Parallel Programming Parameters, Pin Mapping, and Commands 25.5.1 Signal Names 25.6 Parallel Programming 25.6.1 Enter Programming Mode 25.6.2 Considerations for Efficient Programming 25.6.3 Chip Erase 25.6.4 Programming the Flash 25.6.5 Programming the EEPROM 25.6.6 Reading the Flash 25.6.7 Reading the EEPROM 25.6.8 Programming the Fuse Low Bits 25.6.9 Programming the Fuse High Bits 25.6.10 Programming the Extended Fuse Bits 25.6.11 Programming the Lock Bits 25.6.12 Reading the Fuse and Lock Bits 25.6.13 Reading the Signature Bytes 25.6.14 Reading the Calibration Byte 25.6.15 Parallel Programming Characteristics 25.7 Serial Downloading 25.7.1 Serial Programming Pin Mapping 25.7.2 SPI Serial Programming Characteristics 25.8 Programming via the JTAG Interface 25.8.1 Programming Specific JTAG Instructions 25.8.2 AVR_RESET (0xC) 25.8.3 PROG_ENABLE (0x4) 25.8.4 PROG_COMMANDS (0x5) 25.8.5 PROG_PAGELOAD (0x6) 25.8.6 PROG_PAGEREAD (0x7) 25.8.7 Data Registers 25.8.8 Reset Register 25.8.9 Programming Enable Register 25.8.10 Programming Command Register 25.8.11 Flash Data Byte Register 25.8.12 Programming Algorithm 25.8.13 Entering Programming Mode 25.8.14 Leaving Programming Mode 25.8.15 Performing Chip Erase 25.8.16 Programming the Flash 25.8.17 Reading the Flash 25.8.18 Programming the EEPROM 25.8.19 Reading the EEPROM 25.8.20 Programming the Fuses 25.8.21 Programming the Lock Bits 25.8.22 Reading the Fuses and Lock Bits 25.8.23 Reading the Signature Bytes 25.8.24 Reading the Calibration Byte 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 Speed Grades 26.4 Clock Characterizations 26.4.1 Calibrated Internal RC Oscillator Accuracy 26.4.2 External Clock Drive Waveforms 26.4.3 External Clock Drive 26.5 System and Reset Characterizations 26.6 Standard Power-on Reset 26.7 Enhanced Power-on Reset 26.8 Brown-out Detection 26.9 SPI Timing Characteristics 26.10 ADC Characteristics – Preliminary Data 27. Typical Characteristics 27.1 Active Supply Current 27.2 Idle Supply Current 27.3 Supply Current of I/O modules 27.3.1 Example 27.4 Power-down Supply Current 27.5 Power-save Supply Current 27.6 Standby Supply Current 27.7 Pin Pull-up 27.8 Pin Driver Strength 27.9 Pin Threshold and Hysteresis 27.10 Internal Oscillator Speed 27.11 Current Consumption of Peripheral Units 27.12 Current Consumption in Reset and Reset Pulswidth 28. Register Summary 29. Instruction Set Summary 30. Ordering Information 30.1 ATmega325P 30.2 ATmega3250P 31. Packaging Information 31.1 64A 31.2 64M1 31.3 100A 32. Errata 32.1 ATmega325P rev. A 32.2 ATmega325P rev. B 32.3 ATmega325P rev. C 32.4 ATmega3250P rev. A 32.5 ATmega3250P rev. B 32.6 ATmega3250P rev. C 33. Datasheet Revision History 33.1 Rev.8023F– 07/09 33.2 Rev.8023E– 06/08 33.3 Rev.8023D – 08/07 33.4 Rev.8023C – 08/07 33.5 Rev.8023B – 08/07 33.6 Rev.8023A – 12/06 Table of Contents