Datasheet ATmega165, ATmega165V - Preliminary Summary (Atmel) - 4

ATmega165/V
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega165 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial program- mable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue function- ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power- save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscil- lator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Soft- ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega165 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits.
4
2573GS–AVR–07/09 Document Outline Features Pin Configurations Disclaimer Overview Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) Port G (PG4..PG0) RESET XTAL1 XTAL2 AVCC AREF Register Summary Instruction Set Summary Ordering Information Packaging Information 64A 64M1 Errata ATmega165 Rev A Datasheet Revision History Changes from Rev. 2573F-08/06 to Rev. 2573G-07/09 Changes from Rev. 2573E-07/06 to Rev. 2573F-08/06 Changes from Rev. 2573D-03/06 to Rev. 2573E-07/06 Changes from Rev. 2573C-03/06 to Rev. 2573D-03/06 Changes from Rev. 2573B-03/05 to Rev. 2573C-02/06 Changes from Rev. 2573A-06/04 to Rev. 2573B-03/05