Datasheet AT90USB82, AT90USB162 - Complete (Atmel) - 10

conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
10 AT90USB82/162
7707F–AVR–11/10 Document Outline Features 1. Pin Configurations 2. Overview 2.1 Block Diagram 2.2 Pin Descriptions 3. About Code Examples 4. AVR CPU Core 4.1 Introduction 4.2 Architectural Overview 4.3 ALU – Arithmetic Logic Unit 4.4 Status Register 4.5 General Purpose Register File 4.6 Stack Pointer 4.7 Instruction Execution Timing 4.8 Reset and Interrupt Handling 5. AVR AT90USB82/162 Memories 5.1 In-System Reprogrammable Flash Program Memory 5.2 SRAM Data Memory 5.3 EEPROM Data Memory 5.4 I/O Memory 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution 6.2 Clock Switch 6.3 Clock Sources 6.4 Low Power Crystal Oscillator 6.5 Calibrated Internal RC Oscillator 6.6 External Clock 6.7 Clock Output Buffer 6.8 System Clock Prescaler 6.9 PLL 7. Power Distribution 8. Power Management and Sleep Modes 8.1 Idle Mode 8.2 Power-down Mode 8.3 Power-save Mode 8.4 Standby Mode 8.5 Extended Standby Mode 8.6 Power Reduction Register 8.7 Minimizing Power Consumption 9. System Control and Reset 9.1 Resetting the AVR 9.2 Reset Sources 9.3 Power-on Reset 9.4 External Reset 9.5 Brown-out Detection 9.6 Watchdog Reset 9.7 USB Reset 9.8 Internal Voltage Reference 9.9 Watchdog Timer 10. Interrupts 10.1 Interrupt Vectors in AT90USB82/162 11. I/O-Ports 11.1 Introduction 11.2 Ports as General Digital I/O 11.3 Alternate Port Functions 11.4 Register Description for I/O-Ports 12. External Interrupts 13. Timer/Counter0 and Timer/Counter1 Prescalers 14. 8-bit Timer/Counter0 with PWM 14.1 Overview 14.2 Timer/Counter Clock Sources 14.3 Counter Unit 14.4 Output Compare Unit 14.5 Compare Match Output Unit 14.6 Modes of Operation 14.7 Timer/Counter Timing Diagrams 14.8 8-bit Timer/Counter Register Description 15. 16-bit Timer/Counter 1 with PWM 15.1 Overview 15.2 Accessing 16-bit Registers 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Input Capture Unit 15.6 Output Compare Units 15.7 Compare Match Output Unit 15.8 Modes of Operation 15.9 Timer/Counter Timing Diagrams 15.10 16-bit Timer/Counter Register Description 16. Serial Peripheral Interface – SPI 16.1 SS Pin Functionality 16.2 Data Modes 17. USART 17.1 Overview 17.2 Clock Generation 17.3 Frame Formats 17.4 USART Initialization 17.5 Data Transmission – The USART Transmitter 17.6 Data Reception – The USART Receiver 17.7 Asynchronous Data Reception 17.8 Multi-processor Communication Mode 17.9 Hardware Flow Control 17.10 USART Register Description 17.11 Examples of Baud Rate Setting 18. USART in SPI Mode 18.1 Overview 18.2 Clock Generation 18.3 SPI Data Modes and Timing 18.4 Frame Formats 18.5 Data Transfer 18.6 USART MSPIM Register Description 18.7 AVR USART MSPIM vs. AVR SPI 19. USB controller 19.1 Features 19.2 Block Diagram 19.3 Typical Application Implementation 19.4 General Operating Modes 19.5 Power modes 19.6 Memory management 19.7 PAD suspend 19.8 D+/D- Read/write 19.9 Registers description 19.10 USB Software Operating modes 20. USB Device Operating modes 20.1 Introduction 20.2 Power-on and reset 20.3 Endpoint reset 20.4 USB reset 20.5 Endpoint selection 20.6 Endpoint activation 20.7 Address Setup 20.8 Suspend, Wake-up and Resume 20.9 Detach 20.10 Remote Wake-up 20.11 STALL request 20.12 CONTROL endpoint management 20.13 OUT endpoint management 20.14 IN endpoint management 20.15 Isochronous mode 20.16 Overflow 20.17 Interrupts 20.18 Registers 21. PS/2 21.1 Characteristics 22. Analog Comparator 23. Boot Loader Support – Read-While-Write Self-Programming 23.1 Boot Loader Features 23.2 Application and Boot Loader Flash Sections 23.3 Read-While-Write and No Read-While-Write Flash Sections 23.4 Boot Loader Lock Bits 23.5 Entering the Boot Loader Program 23.6 Addressing the Flash During Self-Programming 23.7 Self-Programming the Flash 24. debugWIRE On-chip Debug System 24.1 Features 24.2 Overview 24.3 Physical Interface 24.4 Software Break Points 24.5 Limitations of debugWIRE 24.6 debugWIRE Related Register in I/O Memory 25. Memory Programming 25.1 Program And Data Memory Lock Bits 25.2 Fuse Bits 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Parallel Programming Parameters, Pin Mapping, and Commands 25.6 Parallel Programming 25.7 Serial Downloading 25.8 Serial Programming Pin Mapping 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 External Clock Drive Waveforms 26.4 External Clock Drive 26.5 Maximum speed vs. VCC 26.6 SPI Timing Characteristics 26.7 Hardware Boot EntranceTiming Characteristics 27. AT90USB82/162 Typical Characteristics – Preliminary Data 27.1 Input Voltage Levels 27.2 Output Voltage Levels 27.3 I/O Pull-up Current 27.4 Power-down Supply Current 27.5 Idle Supply Current 27.6 Active Supply Current 27.7 Reset Supply Current 27.8 Bandgap Voltage 27.9 USB Regulator 27.10 Power-On Reset 27.11 BOD Levels 27.12 Watchdog Timer Frequency 27.13 Internal RC Oscillator Frequency 28. Register Summary 29. Instruction Set Summary 30. Ordering Information 31. Packaging Information 31.1 QFN32 31.2 TQFP32 32. Errata 32.1 AT90USB162 Errata History 32.2 AT90USB82 Errata History 33. Datasheet Revision History for AT90USB82/162 33.1 Rev. 7707F – 11/10 33.2 Rev. 7707E – 11/08 33.3 Rev. 7707D 33.4 Rev. 7707C 33.5 Rev. 7707B 33.6 Rev. 7707A Table of Contents