Datasheet AT90PWM2, AT90PWM3, AT90PWM2B, AT90PWM3B - Complete (Atmel) - 7

AT90PWM2/3/2B/3B Table 3-1.
Pin out description (Continued)
S024 Pin SO32 Pin QFN32 Pin Number Number Number Mnemonic Type Name, Function & Alternate Function
XTAL2: XTAL OuTput 11 15 11 PE2 I/O ADC0 (Analog Input Channel 0) 1. PSCOUT10 & PSCOUT11 are not present on 24 pins package
4. Overview
The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
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4317K–AVR–03/2013 Document Outline Features 1. History 2. Disclaimer 3. Pin Configurations 3.1 Pin Descriptions 4. Overview 4.1 Block Diagram 4.2 Pin Descriptions 4.2.1 VCC 4.2.2 GND 4.2.3 Port B (PB7..PB0) 4.2.4 Port C (PC7..PC0) 4.2.5 Port D (PD7..PD0) 4.2.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2 4.2.7 AVCC 4.2.8 AREF 4.3 About Code Examples 5. AVR CPU Core 5.1 Introduction 5.2 Architectural Overview 5.3 ALU – Arithmetic Logic Unit 5.4 Status Register 5.5 General Purpose Register File 5.5.1 The X-register, Y-register, and Z-register 5.6 Stack Pointer 5.7 Instruction Execution Timing 5.8 Reset and Interrupt Handling 5.8.1 Interrupt Behavior 5.8.2 Interrupt Response Time 6. Memories 6.1 In-System Reprogrammable Flash Program Memory 6.2 SRAM Data Memory 6.2.1 SRAM Data Access Times 6.3 EEPROM Data Memory 6.3.1 EEPROM Read/Write Access 6.3.2 The EEPROM Address Registers – EEARH and EEARL 6.3.3 The EEPROM Data Register – EEDR 6.3.4 The EEPROM Control Register – EECR 6.3.5 Preventing EEPROM Corruption 6.4 I/O Memory 6.5 General Purpose I/O Registers 6.5.1 General Purpose I/O Register 0 – GPIOR0 6.5.2 General Purpose I/O Register 1 – GPIOR1 6.5.3 General Purpose I/O Register 2 – GPIOR2 6.5.4 General Purpose I/O Register 3– GPIOR3 7. System Clock 7.1 Clock Systems and their Distribution 7.1.1 CPU Clock – clkCPU 7.1.2 I/O Clock – clkI/O 7.1.3 Flash Clock – clkFLASH 7.1.4 PLL Clock – clkPLL 7.1.5 ADC Clock – clkADC 7.2 Clock Sources 7.3 Default Clock Source 7.4 Low Power Crystal Oscillator 7.5 Calibrated Internal RC Oscillator 7.6 PLL 7.6.1 Internal PLL for PSC 7.6.2 PLL Control and Status Register – PLLCSR 7.7 128 kHz Internal Oscillator 7.8 External Clock 7.9 Clock Output Buffer 7.10 System Clock Prescaler 7.10.1 Clock Prescaler Register – CLKPR 8. Power Management and Sleep Modes 8.1 Sleep Mode Control Register – SMCR 8.2 Idle Mode 8.3 ADC Noise Reduction Mode 8.4 Power-down Mode 8.5 Standby Mode 8.6 Power Reduction Register 8.6.1 Power Reduction Register - PRR 8.7 Minimizing Power Consumption 8.7.1 Analog to Digital Converter 8.7.2 Analog Comparator 8.7.3 Brown-out Detector 8.7.4 Internal Voltage Reference 8.7.5 Watchdog Timer 8.7.6 Port Pins 8.7.7 On-chip Debug System 9. System Control and Reset 9.0.1 Resetting the AVR 9.0.2 Reset Sources 9.0.3 Power-on Reset 9.0.4 External Reset 9.0.5 Brown-out Detection 9.0.6 Watchdog Reset 9.0.7 MCU Status Register – MCUSR 9.1 Internal Voltage Reference 9.1.1 Voltage Reference Enable Signals and Start-up Time 9.1.2 Voltage Reference Characteristics 9.2 Watchdog Timer 9.2.1 Watchdog Timer Control Register - WDTCSR 10. Interrupts 10.1 Interrupt Vectors in AT90PWM2/2B/3/3B 10.1.1 Moving Interrupts Between Application and Boot Space 10.1.2 MCU Control Register – MCUCR 11. I/O-Ports 11.1 Introduction 11.2 Ports as General Digital I/O 11.2.1 Configuring the Pin 11.2.2 Toggling the Pin 11.2.3 Switching Between Input and Output 11.2.4 Reading the Pin Value 11.2.5 Digital Input Enable and Sleep Modes 11.3 Alternate Port Functions 11.3.1 MCU Control Register – MCUCR 11.3.2 Alternate Functions of Port B 11.3.3 Alternate Functions of Port C 11.3.4 Alternate Functions of Port D 11.3.5 Alternate Functions of Port E 11.4 Register Description for I/O-Ports 11.4.1 Port B Data Register – PORTB 11.4.2 Port B Data Direction Register – DDRB 11.4.3 Port B Input Pins Address – PINB 11.4.4 Port C Data Register – PORTC 11.4.5 Port C Data Direction Register – DDRC 11.4.6 Port C Input Pins Address – PINC 11.4.7 Port D Data Register – PORTD 11.4.8 Port D Data Direction Register – DDRD 11.4.9 Port D Input Pins Address – PIND 11.4.10 Port E Data Register – PORTE 11.4.11 Port E Data Direction Register – DDRE 11.4.12 Port E Input Pins Address – PINE 12. External Interrupts 12.0.1 External Interrupt Control Register A – EICRA 12.0.2 External Interrupt Mask Register – EIMSK 12.0.3 External Interrupt Flag Register – EIFR 13. Timer/Counter0 and Timer/Counter1 Prescalers 13.1 Internal Clock Source 13.2 Prescaler Reset 13.3 External Clock Source 13.4 General Timer/Counter Control Register – GTCCR 14. 8-bit Timer/Counter0 with PWM 14.1 Overview 14.1.1 Definitions 14.1.2 Registers 14.2 Timer/Counter Clock Sources 14.3 Counter Unit 14.4 Output Compare Unit 14.4.1 Force Output Compare 14.4.2 Compare Match Blocking by TCNT0 Write 14.4.3 Using the Output Compare Unit 14.5 Compare Match Output Unit 14.5.1 Compare Output Mode and Waveform Generation 14.6 Modes of Operation 14.6.1 Normal Mode 14.6.2 Clear Timer on Compare Match (CTC) Mode 14.6.3 Fast PWM Mode 14.6.4 Phase Correct PWM Mode 14.7 Timer/Counter Timing Diagrams 14.8 8-bit Timer/Counter Register Description 14.8.1 Timer/Counter Control Register A – TCCR0A 14.8.2 Timer/Counter Control Register B – TCCR0B 14.8.3 Timer/Counter Register – TCNT0 14.8.4 Output Compare Register A – OCR0A 14.8.5 Output Compare Register B – OCR0B 14.8.6 Timer/Counter Interrupt Mask Register – TIMSK0 14.8.7 Timer/Counter 0 Interrupt Flag Register – TIFR0 15. 16-bit Timer/Counter1 with PWM 15.1 Overview 15.1.1 Registers 15.1.2 Definitions 15.2 Accessing 16-bit Registers 15.2.1 Reusing the Temporary High Byte Register 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Input Capture Unit 15.5.1 Input Capture Trigger Source 15.5.2 Noise Canceler 15.5.3 Using the Input Capture Unit 15.6 Output Compare Units 15.6.1 Force Output Compare 15.6.2 Compare Match Blocking by TCNTn Write 15.6.3 Using the Output Compare Unit 15.7 Compare Match Output Unit 15.7.1 Compare Output Mode and Waveform Generation 15.8 Modes of Operation 15.8.1 Normal Mode 15.8.2 Clear Timer on Compare Match (CTC) Mode 15.8.3 Fast PWM Mode 15.8.4 Phase Correct PWM Mode 15.8.5 Phase and Frequency Correct PWM Mode 15.9 Timer/Counter Timing Diagrams 15.10 16-bit Timer/Counter Register Description 15.10.1 Timer/Counter1 Control Register A – TCCR1A 15.10.2 Timer/Counter1 Control Register B – TCCR1B 15.10.3 Timer/Counter1 Control Register C – TCCR1C 15.10.4 Timer/Counter1 – TCNT1H and TCNT1L 15.10.5 Output Compare Register 1 A – OCR1AH and OCR1AL 15.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL 15.10.7 Input Capture Register 1 – ICR1H and ICR1L 15.10.8 Timer/Counter1 Interrupt Mask Register – TIMSK1 15.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1 16. Power Stage Controller – (PSC0, PSC1 & PSC2) 16.1 Features 16.2 Overview 16.3 PSC Description 16.3.1 PSC2 Distinctive Feature 16.3.2 Output Polarity 16.4 Signal Description 16.4.1 Input Description 16.4.2 Output Description 16.5 Functional Description 16.5.1 Waveform Cycles 16.5.2 Running Mode Description 16.5.2.1 Four Ramp Mode 16.5.2.2 Two Ramp Mode 16.5.2.3 One Ramp Mode 16.5.2.4 Center Aligned Mode 16.5.3 Fifty Percent Waveform Configuration 16.6 Update of Values 16.6.1 Value Update Synchronization 16.7 Enhanced Resolution 16.7.1 Frequency distribution 16.7.2 Modes of Operation 16.7.2.1 Normal Mode 16.7.2.2 Enhanced Mode 16.8 PSC Inputs 16.8.1 PSC Retri gger Behaviour versus PSC running modes 16.8.2 Retrigger PSCOUTn0 On External Event 16.8.3 Retrigger PSCOUTn1 On External Event 16.8.3.1 Burst Generation 16.8.4 PSC Input Configuration 16.8.4.1 Filter Enable 16.8.4.2 Signal Polarity 16.8.4.3 Input Mode Operation 16.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait 16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. 16.13 PSC Input Mode 5: Stop signal and Insert Dead-Time 16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. 16.15 PSC Input Mode 7: Halt PSC and Wait for Software Action 16.16 PSC Input Mode 8: Edge Retrigger PSC 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output 16.18.1 Available Input Mode according to Running Mode 16.18.2 Event Capture 16.18.3 Using the Input Capture Unit 16.19 PSC2 Outputs 16.19.1 Output Matrix 16.19.2 PSCOUT22 & PSCOUT23 Selectors 16.20 Analog Synchronization 16.21 Interrupt Handling 16.22 PSC Synchronization 16.22.1 Fault events in Autorun mode 16.23 PSC Clock Sources 16.24 Interrupts 16.24.1 List of Interrupt Vector 16.24.2 PSC Interrupt Vectors in AT90PWM2/2B/3/3B 16.25 PSC Register Definition 16.25.1 PSC 0 Synchro and Output Configuration – PSOC0 16.25.2 PSC 1 Synchro and Output Configuration – PSOC1 16.25.3 PSC 2 Synchro and Output Configuration – PSOC2 16.25.4 Output Compare SA Register – OCRnSAH and OCRnSAL 16.25.5 Output Compare RA Register – OCRnRAH and OCRnRAL 16.25.6 Output Compare SB Register – OCRnSBH and OCRnSBL 16.25.7 Output Compare RB Register – OCRnRBH and OCRnRBL 16.25.8 PSC 0 Configuration Register – PCNF0 16.25.9 PSC 1 Configuration Register – PCNF1 16.25.10 PSC 2 Configuration Register – PCNF2 16.25.11 PSC 0 Control Register – PCTL0 16.25.12 PSC 1 Control Register – PCTL1 16.25.13 PSC 2 Control Register – PCTL2 16.25.14 PSC n Input A Control Register – PFRCnA 16.25.15 PSC n Input B Control Register – PFRCnB 16.25.16 PSC 0 Input Capture Register – PICR0H and PICR0L 16.25.17 PSC 1 Input Capture Register – PICR1H and PICR1L 16.25.18 PSC 2 Input Capture Register – PICR2H and PICR2L 16.26 PSC2 Specific Register 16.26.1 PSC 2 Output Matrix – POM2 16.26.2 PSC0 Interrupt Mask Register – PIM0 16.26.3 PSC1 Interrupt Mask Register – PIM1 16.26.4 PSC2 Interrupt Mask Register – PIM2 16.26.5 PSC0 Interrupt Flag Register – PIFR0 16.26.6 PSC1 Interrupt Flag Register – PIFR1 16.26.7 PSC2 Interrupt Flag Register – PIFR2 17. Serial Peripheral Interface – SPI 17.1 Features 17.2 SS Pin Functionality 17.2.1 Slave Mode 17.2.2 Master Mode 17.2.3 MCU Control Register – MCUCR 17.2.4 SPI Control Register – SPCR 17.2.5 SPI Status Register – SPSR 17.2.6 SPI Data Register – SPDR 17.3 Data Modes 18. USART 18.1 Features 18.2 Overview 18.3 Clock Generation 18.3.1 Internal Clock Generation – Baud Rate Generator 18.3.2 Double Speed Operation (U2X) 18.3.3 External Clock 18.3.4 Synchronous Clock Operation 18.4 Serial Frame 18.4.1 Frame Formats 18.4.2 Parity Bit Calculation 18.5 USART Initialization 18.6 Data Transmission – USART Transmitter 18.6.1 Sending Frames with 5 to 8 Data Bit 18.6.2 Sending Frames with 9 Data Bit 18.6.3 Transmitter Flags and Interrupts 18.6.4 Parity Generator 18.6.5 Disabling the Transmitter 18.7 Data Reception – USART Receiver 18.7.1 Receiving Frames with 5 to 8 Data Bits 18.7.2 Receiving Frames with 9 Data Bits 18.7.3 Receive Complete Flag and Interrupt 18.7.4 Receiver Error Flags 18.7.5 Parity Checker 18.7.6 Disabling the Receiver 18.7.7 Flushing the Receive Buffer 18.8 Asynchronous Data Reception 18.8.1 Asynchronous Clock Recovery 18.8.2 Asynchronous Data Recovery 18.8.3 Asynchronous Operational Range 18.9 Multi-processor Communication Mode 18.9.1 MPCM Protocol 18.9.2 Using MPCM 18.10 USART Register Description 18.10.1 USART I/O Data Register – UDR 18.10.2 USART Control and Status Register A – UCSRA 18.10.3 USART Control and Status Register B – UCSRB 18.10.4 USART Control and Status Register C – UCSRC 18.10.5 USART Baud Rate Registers – UBRRL and UBRRH 18.11 Examples of Baud Rate Setting 19. EUSART (Extended USART) 19.1 Features 19.2 Overview 19.3 Serial Frames 19.3.1 Frame Formats 19.3.2 Parity Bit Calculation 19.3.3 Manchester encoding 19.3.3.1 Manchester frame 19.3.3.2 Manchester decoder 19.3.4 Double Speed Operation (U2X) 19.3.4.1 Manchester Framing error detection 19.4 Configuring the EUSART 19.4.1 Data Transmission – EUSART Transmitter 19.4.2 Sending Frames with 5 to 8 Data Bit 19.4.3 Sending Frames with 9, 13, 14, 15 or 16 Data Bit 19.4.4 Sending 17 Data Bit Frames 19.4.5 Transmitter Flags and Interrupts 19.4.6 Disabling the Transmitter 19.4.7 Data Reception – EUSART Receiver 19.5 Data Reception – EUSART Receiver 19.5.1 Receiving Frames with 5 to 8 Data Bits 19.5.2 Receiving Frames with 9, 13, 14, 15 or 16 Data Bits 19.5.3 Receiving 17 Data Bit Frames 19.5.4 Receive Complete Flag and Interrupt 19.5.5 Receiver Error Flags 19.5.5.1 Parity Checker 19.5.5.2 OverRun 19.6 EUSART Registers Description 19.6.1 USART I/O Data Register – UDR 19.6.2 EUSART I/O Data Register – EUDR 19.6.2.1 UDR/EUDR data access with character size up to 8 bits 19.6.2.2 UDR/EUDR data access with 9 bits per character 19.6.2.3 UDR/EUDR data access from 13 to 17 bits per character 19.6.3 EUSART Control and Status Register A – EUCSRA 19.6.4 EUSART Control Register B – EUCSRB 19.6.5 EUSART Status Register C – EUCSRC 19.6.6 Manchester receiver Baud Rate Registers – MUBRRL and MUBRRH 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Register Description 20.2.1 Analog Comparator 0 Control Register – AC0CON 20.2.2 Analog Comparator 1Control Register – AC1CON 20.2.3 Analog Comparator 2 Control Register – AC2CON 20.2.4 Analog Comparator Status Register – ACSR 20.2.5 Digital Input Disable Register 0 – DIDR0 20.2.6 Digital Input Disable Register 1– DIDR1 21. Analog to Digital Converter - ADC 21.1 Features 21.2 Operation 21.3 Starting a Conversion 21.4 Prescaling and Conversion Timing 21.5 Changing Channel or Reference Selection 21.5.1 ADC Input Channels 21.5.2 ADC Voltage Reference 21.6 ADC Noise Canceler 21.6.1 Analog Input Circuitry 21.6.2 Analog Noise Canceling Techniques 21.6.3 Offset Compensation Schemes 21.6.4 ADC Accuracy Definitions 21.7 ADC Conversion Result 21.8 ADC Register Description 21.8.1 ADC Multiplexer Register – ADMUX 21.8.2 ADC Control and Status Register A – ADCSRA 21.8.3 ADC Control and Status Register B– ADCSRB 21.8.4 ADC Result Data Registers – ADCH and ADCL 21.8.4.1 ADLAR = 0 21.8.4.2 ADLAR = 1 21.8.5 Digital Input Disable Register 0 – DIDR0 21.8.6 Digital Input Disable Register 1– DIDR1 21.9 Amplifier 21.10 Amplifier Control Registers 21.10.1 Amplifier 0 Control and Status register – AMP0CSR 21.10.2 Amplifier 1Control and Status register – AMP1CSR 22. Digital to Analog Converter - DAC 22.1 Features 22.2 Operation 22.3 Starting a Conversion 22.3.1 DAC Voltage Reference 22.4 DAC Register Description 22.4.1 Digital to Analog Conversion Control Register – DACON 22.4.2 Digital to Analog Converter input Register – DACH and DACL 22.4.2.1 DALA = 0 22.4.2.2 DALA = 1 23. debugWIRE On-chip Debug System 23.1 Features 23.2 Overview 23.3 Physical Interface 23.4 Software Break Points 23.5 Limitations of debugWIRE 23.6 debugWIRE Related Register in I/O Memory 23.6.1 debugWire Data Register – DWDR 24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Boot Loader Features 24.2 Application and Boot Loader Flash Sections 24.2.1 Application Section 24.2.2 BLS – Boot Loader Section 24.3 Read-While-Write and No Read-While-Write Flash Sections 24.3.1 RWW – Read-While-Write Section 24.3.2 NRWW – No Read-While-Write Section 24.4 Boot Loader Lock Bits 24.5 Entering the Boot Loader Program 24.5.1 Store Program Memory Control and Status Register – SPMCSR 24.6 Addressing the Flash During Self-Programming 24.7 Self-Programming the Flash 24.7.1 Performing Page Erase by SPM 24.7.2 Filling the Temporary Buffer (Page Loading) 24.7.3 Performing a Page Write 24.7.4 Using the SPM Interrupt 24.7.5 Consideration While Updating BLS 24.7.6 Prevent Reading the RWW Section During Self-Programming 24.7.7 Setting the Boot Loader Lock Bits by SPM 24.7.8 EEPROM Write Prevents Writing to SPMCSR 24.7.9 Reading the Fuse and Lock Bits from Software 24.7.10 Preventing Flash Corruption 24.7.11 Programming Time for Flash when Using SPM 24.7.12 Simple Assembly Code Example for a Boot Loader 24.7.13 Boot Loader Parameters 25. Memory Programming 25.1 Program And Data Memory Lock Bits 25.2 Fuse Bits 25.3 PSC Output Behaviour During Reset 25.3.1 Latching of Fuses 25.4 Signature Bytes 25.4.1 Signature Bytes 25.5 Calibration Byte 25.6 Parallel Programming Parameters, Pin Mapping, and Commands 25.6.1 Signal Names 25.7 Serial Programming Pin Mapping 25.8 Parallel Programming 25.8.1 Enter Programming Mode 25.8.2 Considerations for Efficient Programming 25.8.3 Chip Erase 25.8.4 Programming the Flash 25.8.5 Programming the EEPROM 25.8.6 Reading the Flash 25.8.7 Reading the EEPROM 25.8.8 Programming the Fuse Low Bits 25.8.9 Programming the Fuse High Bits 25.8.10 Programming the Extended Fuse Bits 25.8.11 Programming the Lock Bits 25.8.12 Reading the Fuse and Lock Bits 25.8.13 Reading the Signature Bytes 25.8.14 Reading the Calibration Byte 25.8.15 Parallel Programming Characteristics 25.9 Serial Downloading 25.9.1 Serial Programming Algorithm 25.9.2 Data Polling Flash 25.9.3 Data Polling EEPROM 25.9.4 SPI Serial Programming Characteristics 26. Electrical Characteristics(1) 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 External Clock Drive Characteristics 26.3.1 Calibrated Internal RC Oscillator Accuracy 26.3.2 External Clock Drive Waveforms 26.3.3 External Clock Drive 26.4 Maximum Speed vs. VCC 26.5 PLL Characteristics 26.6 SPI Timing Characteristics 26.7 ADC Characteristics 26.8 DAC Characteristics 26.9 Parallel Programming Characteristics 27. AT90PWM2/2B/3/3B Typical Characteristics 27.1 Active Supply Current 27.2 Idle Supply Current 27.2.1 Using the Power Reduction Register 27.2.1.1 Example 1 27.2.1.2 Example 2 27.2.1.3 Example 3 27.3 Power-Down Supply Current 27.4 Pin Pull-up 27.5 Pin Driver Strength 27.6 Pin Thresholds and Hysteresis 27.7 BOD Thresholds and Analog Comparator Offset 27.8 Analog Reference 27.9 Internal Oscillator Speed 27.10 Current Consumption of Peripheral Units 27.11 Current Consumption in Reset and Reset Pulse width 28. Register Summary 29. Instruction Set Summary 30. Ordering Information 31. Package Information 31.1 SO24 31.2 SO32 31.3 QFN32 32. Errata 32.1 AT90PWM2&3 Rev. A (Mask Revision) 32.2 AT90PWM2B/3B 33. Datasheet Revision History for AT90PWM2/2B/3/3B 33.1 Changes from 4317A- to 4317B 33.2 Changes from 4317B- to 4317C 33.3 Changes from 4317C- to 4317D 33.4 Changes from 4317D to 4317E 33.5 Changes from 4317E to 4317F 33.6 Changes from 4317F to 4317G 33.7 Changes from 4317G to 4317H 33.8 Changes from 4317H to 4317I 33.9 Changes from 4317I to 4317J 33.10 Changes from 4317J to 4317K