Datasheet LT3710 (Analog Devices) - 7

LT3710
U OPERATIO
To generate isolated multiple outputs, most systems use until the ramp signal intersects the feedback error ampli- either multiple secondary windings or cascade regulators fier output VAOUT. The top MOSFET M1 turns on, pulling for each additional output. Multiple secondary windings the switch node voltage to VS. The inductor current of the sacrifice regulation of the auxiliary outputs. Cascaded LT3710 circuit is then charged by VS – VOUT2. The effective regulators require a larger inductor for the main output, on time of this buck circuit ends when the secondary because all of the power is processed in series. voltage becomes zero. The next cycle repeats. By generating the auxiliary output(s) from the secondary The ideal equation for duty cycle of the LT3710 is: winding of the main output, the LT3710 allows for parallel D2 = V processing of the output power. This minimizes the main OUT2/VSP output inductor size and directly regulates the auxiliary where VOUT2 is the auxiliary output voltage, VSP is the output. With synchronous rectification, the system effi- amplitude of the secondary voltage and D2 is the duty ciency is greatly improved. cycle of the switching node voltage VSW, as defined in Figure 2. Refering to the Block Diagram, the LT3710 basic functions V include a voltage amplifier, VA, to regulate the output RESET T voltage to within typically 1.5%, a voltage mode PWM with D1T trailing edge synchronization and leading edge modula- TRANSFORMER V V SECONDARY VOLTAGE S SP tion, a current limit amplifier, CA1, and high speed syn- chronous switch drivers. SYNC SIGNAL VRESET During normal operation (see Figure 2), a switching cycle RAMP VCSET VAOUT begins at the falling edge of the transformer secondary TGATE voltage VS. The internal oscillator is reset, turning off the top MOSFET M1 and turning on the bottom MOSFET M2. BGATE During this portion of the cycle, the inductor current is IL discharged by the output voltage VOUT2. The transformer T secondary voltage VS will go high during this portion of the SWITCH NODE VSW D2T VSP cycle. Since M1 is off, the switch node voltage V 3710 F02 SW remains zero. The inductor current continues to be dis-
Figure 2. Leading Edge Modulation, Trailing Edge Synchronization
charged by the output voltage VOUT2. This condition lasts
U U W U APPLICATIO S I FOR ATIO Synchronization and Oscillation Frequency Setting
fOSC < (fSL • 0.8) The switching is synchronized to the secondary winding fSL is the low limit of the system switching frequency and falling edge and the synchronization threshold is typically 0.8 is the tolerance of fOSC. 2.5V. The synchronization falling edge triggers an internal For example, a system of 200KHz with 15% tolerance, inverted ramp (see Figure 2) and starts a new switching then f cycle for the leading edge voltage mode PWM. The reason SL = 200k • 85% = 170kHz; and fOSC < (170k • 0.8), f for using leading edge modulation is to keep the trans- OSC should be set below 136kHz. former primary side peak current sensing undisturbed. Once fOSC is determined, CSET can be calculated by CSET = (107250pf/f For proper synchronization, the oscillator frequency should OSC(kHz)) – 50pF. be set lower than the system switching frequency with For fOSC = 100kHz, CSET = 1022.5pF. tolerances taken into account. 3710f 7