Datasheet LTC3901 (Analog Devices) - 7

LTC3901
U U W U APPLICATIO S I FOR ATIO
In the first period, SDRA goes low (followed by DRVA MOSFETs are also kept on for long periods when the going high) and T2 generates a positive voltage at the primary controller enters Burst Mode operation. Both ME LTC3901’s SYNC input. The LTC3901’s ME output then and MF stop switching until the primary controller exits pulls low. Current flows to the load through MOSFET MF, Burst Mode operation. This would also cause the inductor T1’s secondary and L1. current to reverse and the drains to fly high. In the second period, SDRA goes high and T2 provides In both of these situations, the timer and/or current sense approximately 0V at the LTC3901 SYNC input. This causes comparator shuts off the drivers before or immediately the LTC3901’s ME output to go high and both MOSFET ME after the inductor current reverses direction. This prevents and MF to conduct. This is the free-wheeling period with the buildup of inductor energy. T1 secondary winding shorted. In the third period, SDRB goes low (followed by DRVB
Timer
going high) and T2 generates a negative voltage at the The timer circuit (Figure 3) operates by using an external LTC3901’s SYNC input. The LTC3901’s MF output then R-C charging network to program the timeout period. On pulls low. Current flows to the load through MOSFET ME, every transition at the SYNC input, the chip generates a T1’s secondary and L1. 200ns pulse to reset the timer capacitor. If the SYNC signal The last period is also a free-wheeling period like the is missing or incorrect (allowing the timer capacitor volt- second period. Both SDRA and SDRB are high and the age to go high) it shuts off both drivers once the voltage LTC3901 forces both MOSFETs ME and MF to conduct. reaches the timeout threshold. Figure 4 shows the timer waveforms.
External MOSFET Protection
VCC A programmable timer and two differential input current 16 sense comparators are included in the LTC3901 for pro- LTC3901 VCC RTMR 32k tection of the external MOSFETs during power down and TMR TIMER 7 Burst Mode® operation. The chip also shuts off the TIMEOUT Z C TMR TMR 0.5 • V 470pF MOSFETs if V CC CC < 4.1V or if the synchronization sequence is incorrect. R1 180k When the primary controller is powering down, the R2 TIMER MTMR RESET LTC3901 continues to operate by drawing power from the 45k VCC bypass cap, CVCC. The primary controller synchro- 3901 F03 nous output stops switching and the LTC3901 SYNC input goes to 0V. Both ME and MF remain on and the decreasing
Figure 3. Timer Circuit
inductor current continues to flow into the load. Once the inductor current decreases to zero, it reverses direction, SYNC 0V discharging the output capacitor COUT to GND through both MOSFETs. At the same time, the CVCC voltage contin- ME ues to drop. When the voltage drops below 4.1V, the LTC3901 shuts down and pulls both ME and MF low. This MF causes the inductor current to stop suddenly and the drain TIMER RESET voltage of both MOSFETs to fly high, due to the buildup of (INTERNAL) inductor energy. In the absence of a protection timer, if the inductor energy is high due to a long period of current TIMER TIMEOUT reversal, the drain voltage can go above the MOSFET’s THRESHOLD voltage rating and cause damage to the MOSFET. 3901 F02 Burst Mode is a registered trademark of Linear Technology Corporation.
Figure 4. Timer Waveforms
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