Datasheet ADM1041A (Analog Devices) - 9

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ADM1041A Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT LIMIT ERROR AMPLIFIER See Figure 13 Current Limit Trim Range2 105 130 % After ISHARE calibration Current Limit Trim Step 1.1 % Current Limit Trim Step 26.5 mV 2.0 ≤ VSHARE ≤ 2.8 V typ, 5 bits, 31 steps. Reg 04h[7:3]. See Table 13. Transconductance 100 200 300 μA/V ICCMP = ±20 μA. See Figure 12. Output Source Current 40 μA VCCMP = >1 V Output Sink Current 40 μA VCCMP = <VDD – 1 V CURRENT SHARE DRIVER See Figure 15 Output Voltage6 (VDD – 0.4) V RL = 1 kΩ, VSHRS ≤ VDD – 2 V Short Circuit Source Current 55 mA Source Current 15 mA Current at which VOUT does not drop by more than 5% Sink Current 60 100 μA VSHARE = 2.0 V CURRENT SHARE DIFFERENTIAL SENSE See Figure 15 AMPLIFIER VS– Input Voltage 0.5 V Voltage on Pin 20 VSHRS Input Voltage VDD – 2 V Voltage on Pin 23 Input Impedance2 65 100 kΩ VSHRS = 0.5 V, VS− = 0.5 V Gain 1.0 V/V CURRENT SHARE ERROR AMPLIFIER Transconductance, SHRS to SCMP 100 200 300 μA/V ISCMP = ±20 μA Output Source Current 40 μA VSCMP > 1 V Output Sink Current 40 μA VSCMP < VDD – 1 V Input Offset Voltage 40 50 60 mV Master/slave arbitration Share OK Window Comparator Threshold SHRS = 2 V ± SHRTHRESH (Share Drive Error) ±100 mV Reg 04h[1:0] = 00. See Table 13. ±200 mV Reg 04h[1:0] = 01. See Table 13. ±300 mV Reg 04h[1:0] = 10. See Table 13. ±400 mV Reg 04h[1:0] = 11. See Table 13. CURRENT LIMIT Figure 10 Current Limit Control Lower Threshold 1.3 V VCCMP = 0.7 V, VS+ = 1.5 V Current Limit Control Upper Threshold 3.5 V VS+ = 0 V, VSCMP = 0 V CURRENT SHARE CAPTURE VSCMP = 3.5 V. Current Share Capture Range 0.7 1 1.3 % Reg 10h[5:4] = 00. See Table 25. 1.4 2 2.6 % Reg 10h[5:4] = 01. See Table 25. 2.1 3 3.9 % Reg 10h[5:4] = 10. See Table 25. 2.8 4 5.2 % Reg 10h[5:4] = 11. See Table 25. Capture Threshold 0.6 1.0 1.4 V FET OR GATE DRIVE Open-drain N-channel FET Output Low Level (On) 0.4 V IIO = 5 mA 0.8 V IIO = 10 mA Output Leakage Current −5 +5 μA REVERSE VOLTAGE COMPARATOR, FS, FD VCS− = FS Common-Mode Range 0.25 2.0 (VDD – 2) V Voltage set by CS resistor divider. Voltage on CS− pin, TA = 25°C. Rev. 0 | Page 9 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE