Datasheet LT1425 (Analog Devices) - 9

LT1425
U OPERATION
regulation. See Applications Information section for fur-
Effects of Variable Enable Period
ther details. It should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. This can vary from
Enable Delay
the fixed “minimum enable time” described to a maximum When the output switch shuts off, the flyback pulse of roughly the OFF switch time minus the enable delay appears. However, it takes a finite time until the trans- time. Certain parameters of flyback amp behavior will then former primary side voltage waveform approximately rep- be directly affected by the variable enable period. These resents the output voltage. This is partly due to rise time include effective transconductance and VC node slew rate. on the VSW node, but more importantly due to transformer leakage inductance. The latter causes a voltage spike on
LOAD COMPENSATION THEORY
the primary side not directly related to output voltage. (Some time is also required for internal settling of the The LT1425 uses the flyback pulse to obtain information feedback amplifier circuitry.) about the isolated output voltage. A potential error source is caused by transformer secondary current flow through In order to maintain immunity to these phenomena, a fixed the real life nonzero impedances of the output rectifier, delay is introduced between the switch turn-off command transformer secondary and output capacitor. This has and the enabling of the feedback amplifier. This is termed been represented previously by the expression (ISEC)(ESR). “enable delay.” In certain cases where the leakage spike is However, it is generally more useful to convert this expres- not sufficiently settled by the end of the enable delay sion to an effective output impedance. Because the sec- period, regulation error may result. See Applications ondary current only flows during the off portion of the duty Information section for further details. cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty
Collapse Detect
cycle. That is, Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a 1 collapse detect comparator, that compares the flyback R ) OUT = ESR DC OFF voltage (RREF referred) to a fixed reference, nominally where, 80% of VBG. When the flyback waveform drops below this R level, the feedback amplifier is disabled. This action OUT = Effective supply output impedance accommodates both continuous and discontinuous mode ESR = Lumped secondary impedance operation. DC OFF = OFF duty cycle
Minimum Enable Time
Expressing this in terms of the ON duty cycle, remember- The feedback amplifier, once enabled, stays enabled for a ing DC OFF = 1 – DC, fixed minimum time period termed “minimum enable 1 time.” This prevents lock-up, especially when the output R voltage is abnormally low, e.g., during start-up. The mini- ) OUT = ESR 1 – DC mum enable time period ensures that the VC node is able DC = ON duty cycle to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper In less critical applications, or if output load current operation. The “minimum enable time” often determines remains relatively constant, this output impedance error the low load level at which output voltage regulation is lost. may be judged acceptable and the external RFB resistor See Applications Information section for details. value adjusted to compensate for nominal expected error. In more demanding applications, output impedance error 9