Datasheet LT1725 (Analog Devices) - 9

LT1725
U OPERATIO
The LT1725 is a current mode switcher controller IC The relatively high gain in the overall loop will then cause designed specifically for the isolated flyback topology. The the voltage at the FB pin to be nearly equal to the bandgap Block Diagram shows an overall view of the system. Many reference VBG. The relationship between VFLBK and VBG of the blocks are similar to those found in traditional may then be expressed as: designs, including: Internal Bias Regulator, Oscillator, Logic, Current Amplifier and Comparator, Driver and Out- R ( 1+R )2 V = V put Switch. The novel sections include a special Flyback FLBK BG R2 Error Amplifier and a Load Compensation mechanism. Combination with the previous V Also, due to the special dynamic requirements of flyback FLBK expression yields an expression for V control, the Logic system contains additional functionality OUT in terms of the internal reference, not found in conventional designs. programming resistors, transformer turns ratio and diode forward voltage drop: The LT1725 operates much the same as traditional current mode switchers, the major difference being a different R ( 1+R2) type of error amplifier that derives its feedback informa- V = V N ( )– V –I •ESR OUT BG ST F SEC R2 tion from the flyback pulse. Due to space constraints, this discussion will not reiterate the basics of current mode Additionally, it includes the effect of nonzero secondary switcher/controllers and isolated flyback converters. A output impedance, which is discussed below in further good source of information on these topics is Application detail, see Load Compensation Theory. The practical as- Note AN19. pects of applying this equation for VOUT are found in the Applications Information section.
ERROR AMPLIFIER—PSEUDO DC THEORY
So far, this has been a pseudo-DC treatment of flyback Please refer to the simplified diagram of the Flyback Error error amplifier operation. But the flyback signal is a pulse, Amplifier. Operation is as follows: when MOSFET output not a DC level. Provision must be made to enable the switch M1 turns off, its drain voltage rises above the V flyback amplifier only when the flyback pulse is present. IN rail. The amplitude of this flyback pulse as seen on the third This is accomplished by the dotted line connections to the winding is given as: block labeled “ENAB”. Timing signals are then required to enable and disable the flyback amplifier. (V + V +I •ESR) V OUT F SEC FLBK = NST
ERROR AMPLIFIER—DYNAMIC THEORY
V There are several timing signals which are required for F = D1 forward voltage proper LT1725 operation. Please refer to the Timing ISEC = transformer secondary current Diagram. ESR = total impedance of secondary circuit N
Minimum Output Switch On Time
ST = transformer effective secondary-to-third winding turns ratio The LT1725 affects output voltage regulation via flyback The flyback voltage is then scaled by external resistor pulse action. If the output switch is not turned on at all, divider R1/R2 and presented at the FB pin. This is then there will be no flyback pulse and output voltage informa- compared to the internal bandgap reference by the differ- tion is no longer available. This would cause irregular loop ential transistor pair Q1/Q2. The collector current from Q1 response and start-up/latchup problems. The solution cho- is mirrored around and subtracted from fixed current sen is to require the output switch to be on for an absolute source I minimum time per each oscillator cycle. This in turn estab- FXD at the VC pin. An external capacitor integrates this net current to provide the control voltage to set the lishes a minimum load requirement to maintain regula- current mode trip point. tion. See Applications Information for further details. 1725fa 9