Datasheet LT1737 (Analog Devices) - 10

LT1737
U OPERATIO Enable Delay Minimum Enable Time
When the output switch shuts off, the flyback pulse The feedback amplifier, once enabled, stays enabled for a appears. However, it takes a finite time until the trans- fixed minimum time period termed “minimum enable former primary side voltage waveform approximately rep- time.” This prevents lockup, especially when the output resents the output voltage. This is partly due to finite rise voltage is abnormally low, e.g., during start-up. The mini- time on the MOSFET drain node, but more importantly, mum enable time period ensures that the VC node is able due to transformer leakage inductance. The latter causes to “pump up” and increase the current mode trip point to a voltage spike on the primary side not directly related to the level where the collapse detect system exhibits proper output voltage. (Some time is also required for internal operation. The “minimum enable time” often determines settling of the feedback amplifier circuitry.) the low load level at which output voltage regulation is lost. See Applications Information for details. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turnoff command
Effects of Variable Enable Period
and the enabling of the feedback amplifier. This is termed enable delay. In certain cases where the leakage spike is It should now be clear that the flyback amplifier is enabled not sufficiently settled by the end of the enable delay during only a portion of the cycle time. This can vary from period, regulation error may result. See Application Infor- the fixed “minimum enable time” described to a maximum mation for further details. of roughly the “off” switch time minus the enable delay time. Certain parameters of flyback amp behavior will then
Collapse Detect
be directly affected by the variable enable period. These include effective transconductance and V Once the feedback amplifier is enabled, some mechanism C node slew rate. is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback
LOAD COMPENSATION THEORY
voltage (FB referred) to a fixed reference, nominally 80% The LT1737 uses the flyback pulse to obtain information of VBG. When the flyback waveform drops below this about the isolated output voltage. A potential error source level, the feedback amplifier is disabled. This action is caused by transformer secondary current flow through accommodates both continuous and discontinuous mode the real life nonzero impedances of the output rectifier, operation. T1 VIN IM M1 R1 + FB R3 Q1 Q2 VBG Q3 A1 ISENSE 50k R2 – LOAD COMP I I R M R SENSE OCMP RCMPC 1737 F01
Figure 1. Load Compensation Diagram
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