Datasheet LTC3723 (Analog Devices) - 10

LTC3723-1/LTC3723-2
U OPERATIO
Please refer to the detailed Block Diagrams for this discus-
Programming Driver Dead-Time
sion. The LTC3723-1 and LTC3723-2 are synchronous The LTC3723-1/LTC3723-2 controllers include a feature PWM push-pull controllers. The LTC3723-1 operates with to program the minimum time between the output signals peak pulse-by-pulse current mode control while the on DRVA and DRVB commonly referred to as the driver LTC3723-2 offers voltage mode control operation. They dead-time. This function will come into play if the control- are best suited for moderate to high power isolated power ler is commanded for maximum duty cycle. The dead-time systems where small size and high efficiency are required. is set with an external resistor connected between DPRG The push-pull topology delivers excellent transformer and V utilization and requires only two low side power MOSFET REF (see Figure 1). The nominal regulated voltage on DPRG is 2V. The external resistor programs a current switches. Both controllers generate 180° out of phase which flows into DPRG. The dead-time can be adjusted 0% to < 50% duty cycle drive signals on DRVA and DRVB. from 90ns to 300ns with this resistor. The dead-time can The external MOSFETs are driven directly by these power- also be modulated based on an external current source ful on-chip drivers. The external MOSFETs typically con- that feeds current into DPRG. Care must be taken to limit trol opposite primary windings of a centertapped power the current fed into DPRG to 350µA or less. An internal transformer. The centertap primary winding is connected 10µA current source sets a maximum deadtime if DPRG is to the input DC feed. The secondary of the transformer can floated. The internal current source causes the programmed be configured in different synchronous or nonsynchronous deadtime to vary non-linearly with increasing values of configurations depending on the application needs. RDPRG (see typical performance characteristics). An ex- The duty ratio is controlled by the voltage on COMP. A ternal 200k resistor connected from DPRG to GND will switching cycle commences with the falling edge of the compensate for the internal 10µA current source and internal oscillator clock pulse. The LTC3723-1 attenuates linearize the deadtime delay vs RDPRG characteristic. the voltage on COMP and compares it to the current sense signal to terminate the switching cycle. The LTC3723-2
Powering the LTC3723-1/LTC3723-2
compares the voltage on COMP to a timing ramp to The LTC3723-1/LTC3723-2 utilize an integrated VCC shunt terminate the cycle. The LTC3723-2’s CT waveform can be regulator to serve the dual purposes of limiting the voltage used for this purpose or separate R-C components can be applied to VCC as well as signaling that the chip’s bias connected to RAMP to generate the timing ramp. If the voltage is sufficient to begin switching operation (under voltage on CS exceeds 300mV, the present cycle is termi- voltage lockout). With its typical 10.2V turn-on voltage nated. If the voltage on CS exceeds 600mV, all switching and 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 is stops and a soft-start sequence is initiated. tolerant of loosely regulated input sources such as an auxiliary transformer winding. The V The LTC3723-1 / LTC3723-2 also provide drive signals for CC shunt is capable of sinking up to 40mA of externally applied current. The secondary side synchronous rectifier MOSFETs. Synchro- UVLO turn-on and turn-off thresholds are derived from an nous rectification improves converter efficiency, espe- internally trimmed reference making them extremely ac- cially as the output voltages drop. Independent turn-off curate. In addition, the LTC3723-1/LTC3723-2 exhibits control of the synchronous rectifiers is provided via SPRG VREF in order to optimize the benefit of the synchronous recti- fiers. A resistor from SPRG to GND sets the desired turn RDPRG 10 off delay. DPRG µA A host of other features including an error amplifier, + + TURN-ON OPTIONAL 200k system UVLO programming, adjustable leading edge blank- V 2V OUTPUT 2.5V – ing, slope compensation and programmable dead-time – 372312 F01 provide flexibility for a variety of applications.
Figure 1. Delay Timeout Circuitry
372312f 10