Datasheet LT3825 (Analog Devices) - 6

LT3825
TYPICAL PERFORMANCE CHARACTERISTICS Minimum PG On-Time vs Temperature PG Delay Time vs Temperature Enable Delay Time vs Temperature
340 300 320 RtON(MIN) = 158k RENDLY = 90k 330 250 300 320 RPGDLY = 27.4k 200 280 310 (ns) (ns) 300 150 (ns) 260 t ED t ON(MIN) 290 t PGDLY RPGDLY = 16.9k 100 240 280 50 220 270 260 0 200 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3825 G19 3825 G20 3825 G21
PIN FUNCTIONS SG (Pin 1):
Synchronous Gate Drive Output. This pin pro-
SYNC (Pin 5):
Pin for synchronizing the internal oscilla- vides an output signal for a secondary-side synchronous tor with an external clock. The positive edge on a pulse switch. Large dynamic currents may flow during voltage causes the oscillator to discharge causing PG to go low transitions. See the Applications Information for details. (off) and SG high (on). The sync threshold is typically
V
1.53V. See Applications Information for details. Tie to
CC (Pin 2):
Supply Voltage Pin. Bypass this pin to ground with a 4.7µF capacitor or more. This pin has a ground if unused. 19.5V clamp to ground. VCC has an undervoltage lockout
SFST (Pin 6):
This pin, in conjunction with a capacitor to function that turns the part on when VCC is approximately ground, controls the ramp-up of peak primary current as 15.3V and off at 9.7V. In a conventional “trickle-charge” sensed through the sense resistor. This is used to control bootstrapped configuration, the VCC supply current converter inrush current at start-up. The VC pin voltage increases significantly during turn-on causing a benign cannot exceed the SFST pin voltage, so as SFST increases, relaxation oscillation action on the VCC pin if the part does the maximum voltage on VC increases commensurately, not start normally. allowing higher peak currents. Total VC ramp time is ap-
t
proximately 70ms per µF of capacitance. Leave pin open
ON (Pin 3):
Pin for external programming resistor to set the minimum time that the primary switch is on for each if not using the soft-start function. cycle. Minimum turn-on facilitates the isolated feedback
OSC (Pin 7):
This pin in conjunction with an external method. See Applications Information for details. capacitor defines the controller oscillator frequency. The
ENDLY (Pin 4):
Pin for external programming resistor to frequency is approximately 100kHz • 100/COSC(pF). set enable delay time. The enable delay time disables the
FB (Pin 8):
Pin for the feedback node for the power supply feedback amplifier for a fixed time after the turn-off of the feedback amplifier. Feedback is usually sensed via a third primary-side MOSFET. This allows the leakage inductance winding and enabled during the flyback period. This pin voltage spike to be ignored for flyback voltage sensing. also sinks additional current to compensate for load cur- See Applications Information for details. rent variation as set by the RCMP pin. Keep the Thevenin equivalent resistance of the feedback divider at roughly 3k. 3525fe 6 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts