Datasheet LT8310 (Analog Devices) - 9

LT8310
pin FuncTions UVLO (Pin 1):
System Undervoltage Lockout Input.
SS (Pin 8):
Soft-Start Input. Program start and hiccup Program the system falling UVLO threshold (minimum timing by tying an external capacitor between SS and GND. VIN voltage) with a resistive voltage divider from VIN to During normal soft-start this pin sources 50µA. During this pin. The pin voltage is compared internally to an ac- faults and initial start, a 6mA (typ) current sink discharges curate 1.22V threshold. Program the system rising UVLO this pin to 0.27V (typ). The GATE pin is shut off until VSS hysteresis via this pin’s 5.7µA hysteretic current and the ≥ 1V. After an overcurrent shutdown, the pin sources only values of the external resistors. The device is shut down 5µA until VSS ≥ 1V, which provides an extended wake-up below the UVLO threshold and draws 1µA or less from VIN period that reduces power dissipation during repeated when VUVLO ≤ 0.36V (min). The UVLO pin can withstand start-up retries (hiccup mode). Switching frequency and 100V maximum. duty cycle are folded back until SS > 2.5V. Above 1V, the
OVLO (Pin 3):
System Overvoltage Lockout Input. Program pin sources 50µA until charged to an internal 3V clamp. the system rising OVLO threshold (maximum VIN voltage)
VC (Pin 9):
Transconductance Error Amp Output. Compen- with a resistive voltage divider from VIN to this pin. The sate the converter loop at this pin with an external series pin voltage is compared internally to an accurate 1.25V resistor and capacitor to GND in feedback applications. threshold. Exceeding the OVLO threshold sets the fault In opto-isolated feedback applications, compensation is latch and forces a system shutdown. generally done on the secondary side (see the Applica-
DFILT (Pin 5):
Duty Cycle Loop Filter Pin. Set the duty tions Information section). In duty mode control applica- cycle loop filter pole by connecting a capacitor to GND tions that have no output voltage feedback, leave this pin from this pin in both duty mode and current mode ap- unconnected. plications. Consult the Applications Information section
FBX (Pin 10):
Feedback Input and Mode Control. Standard to choose the capacitor value to reduce load step ringing input for nonisolated applications that require voltage in duty mode control applications. Do not float this pin, a feedback. Program output voltage with a resistive voltage capacitor is required. divider to compare to the internal 1.6V reference for positive
RT (Pin 6):
Switching Period Set Input. Set the oscillator output applications, or to the –0.8V reference for negative switching period (frequency) via a resistor to GND from output applications. When –0.2V < VFBX < 0.3V, duty mode this pin, typically 20k to 100k for 2µs to 10µs (500kHz to controls the GATE pin, otherwise FBX is assumed to be 100kHz). In applications where an external clock drives the in control. FBX exceeding its reference by 7.5% ends the SYNC pin, program the switching period to the expected switching cycle in progress without triggering a system SYNC frequency value. Place the resistor close to the pin reset. Tie FBX to GND if duty mode only is desired. and minimize stray capacitance. Do not leave the RT pin
SOUT (Pin 11):
Synchronization Output. Pulse transformer open. driver for applications with synchronous secondary-side
SYNC (Pin 7):
External Clock Input. Drive this pin with control, complementary to GATE. The SOUT falling edge an external fixed-frequency clock signal to synchronize leads GATE turn-on by 240ns (typ), and the rising edge switching to it. The SYNC falling edge is automatically trails GATE turn off by 12ns (typ). Actively pulled to INTVCC detected and converted to a pulse that starts the minimum during shutdown. off-time of the duty cycle. The SYNC pulse low and highs
NC (Pin 12):
No Internal Connection. Connect to GND. times must both be ≥250ns. Select an RT resistor that programs the internal switch frequency to the external SYNC frequency to keep the maximum duty cycle limit accurate. When VSS < 1V, the SYNC pin is ignored. 8310f For more information www.linear.com/LT8310 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Typical Applications Package Description Typical Application Related Parts