Datasheet LTC1871X (Analog Devices) - 10

LTC1871X
OPERATION
MOSFET RDS(ON). If the ITH pin drops below 0.30V, the When an external clock signal drives the MODE/SYNC Burst Mode comparator B1 will turn off the power MOSFET pin at a rate faster than the chip’s internal oscillator, the and scale back the quiescent current of the IC to 250µA oscillator will synchronize to it. In this synchronized mode, (sleep mode). In this condition, the load current will be Burst Mode operation is disabled. The constant frequency supplied by the output capacitor until the ITH voltage rises associated with synchronized operation provides a more above the 50mV hysteresis of the burst comparator. At controlled noise spectrum from the converter, at the ex- light loads, short bursts of switching (where the average pense of overall system efficiency of light loads. inductor current is 20% of its maximum value) followed When the oscillator’s internal logic circuitry detects a by long periods of sleep will be observed, thereby greatly synchronizing signal on the MODE/SYNC pin, the in- improving converter efficiency. Oscilloscope waveforms ternal oscillator ramp is terminated early and the slope illustrating Burst Mode operation are shown in Figure 3. compensation is increased by approximately 30%. As
Pulse-Skip Mode Operation
a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of With the MODE/SYNC pin tied to a DC voltage above 2V, the IC be programmed to be about 75% of the external Burst Mode operation is disabled. The internal, 0.525V clock frequency. Attempting to synchronize to too high an buffered ITH burst clamp is removed, allowing the ITH external frequency (above 1.3fO) can result in inadequate pin to directly control the current comparator from no slope compensation and possible subharmonic oscillation load to full load. With no load, the ITH pin is driven below (or jitter). 0.30V, the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode The external clock signal must exceed 2V for at least 25ns, of operation are shown in Figure 4. and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the V rising edge of the external clock signal. IN = 3.3V MODE/SYNC = 0V VOUT = 5V (Burst Mode OPERATION) IOUT = 500mA VOUT 2V TO 7V 50mV/DIV MODE/ SYNC tMIN = 25ns 0.8T T T = 1/fO IL 5A/DIV GATE D = 40% 10µs/DIV 1871x F03
Figure 3. LTC1871X Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current
IL 1871x F05 VIN = 3.3V MODE/SYNC = INTVCC VOUT = 5V (PULSE-SKIP MODE)
Figure 5. MODE/SYNC Clock Input and Switching
IOUT = 500mA
Waveforms for Synchronized Operation
VOUT 50mV/DIV IL 5A/DIV 2µs/DIV 1871x F04
Figure 4. LTC1871X Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTVCC)
1871xf 10 For more information www.linear.com/LTC1871X Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts