Datasheet AD5749 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Industrial Current Out Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges |
| Páginas / Página | 28 / 7 — Data Sheet. AD5749. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter. Rating. … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 553 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD5749. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter. Rating. ESD CAUTION
Versión de texto del documento
Data Sheet AD5749 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a
Table 4.
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond AVDD to GND −0.3 V to +58 V the maximum operating conditions for extended periods may DVCC to GND −0.3 V to +7 V affect product reliability. Digital Inputs to GND −0.3 V to DVCC + 0.3 V, or 7 V (whichever is less)
ESD CAUTION
Digital Outputs to GND −0.3 V to DVCC + 0.3 V, or 7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V IOUT to GND −0.3 V to AVDD Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 32-Lead LFCSP Package θJA Thermal Impedance1 42°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 1 Simulated data based on a JEDEC 2S2P test board with thermal vias. Rev. D | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE
TA = 25°C, unless otherwise noted. Transient currents of up to Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a
Table 4.
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond AVDD to GND −0.3 V to +58 V the maximum operating conditions for extended periods may DVCC to GND −0.3 V to +7 V affect product reliability. Digital Inputs to GND −0.3 V to DVCC + 0.3 V, or 7 V (whichever is less)
ESD CAUTION
Digital Outputs to GND −0.3 V to DVCC + 0.3 V, or 7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V IOUT to GND −0.3 V to AVDD Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 32-Lead LFCSP Package θJA Thermal Impedance1 42°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 1 Simulated data based on a JEDEC 2S2P test board with thermal vias. Rev. D | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE