Datasheet TPS2410, TPS2411 (Texas Instruments) - 7

link to page 22 link to page 18
TPS2410 TPS2411 www.ti.com
.. SLVS727C – NOVEMBER 2006 – REVISED JUNE 2009
DETAILED DESCRIPTION
The following descriptions refer to the pinout and the functional block diagram.
A, C:
The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(AC) exceeds 10 mV. Both devices provide a strong GATE pull-down when V(AC) is less than the programmable fast turn-off threshold. The TPS2410 has a soft pull-down when V(AC) is less than 10 mV but above the fast turn-off threshold. Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excess differential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a small current flows out of A. Protect the internal circuits with an external clamp if C can be more than 6 V lower than A. A small signal clamp diode and 1-kΩ resistor, or circuit per Figure 18 are suitable. The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is referenced to A. Some charge pump current appears on A due to this topology. The A and C pins should be Kelvin connected to the MOSFET source and drain. A and C connections should also be short and low impedance, with special attention to the A connection. Residual noise from the charge pump can be reduced with a bypass capacitor at A if the application permits.
BYP:
BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits and GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pF ceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering. Shorting this pin to a voltage below A damages the TPS2410/11.
FLTR:
The internal fast comparator input may be filtered by placing a small capacitor from FLTR to A. This is useful in situations where the ambient noise or transients might falsely trigger a MOSFET turnoff. While C(FLTR) will suppress small transients, large voltage reversals will see relatively small additional turn-off delay. FLTR is clamped to C and should only be used with a capacitor as shown in Figure 14. Connections to FLTR should be short and direct to minimize parasitic capacitive loading and crosstalk. The filter pin may not be shorted to any other voltage.
FLTB:
The FLTB pin is the open-drain fault output. FLTB sinks current when the MOSFET should be enabled, but either there is no GATE voltage, V(AC) is greater than 0.4 V with GATE driven ON, the internal UVLO is not satisfied. FLTB has a 3-ms deglitch filter on the falling edge to prevent transients from creating false signals. FLTB may not be valid at voltages below the internal VDD UVLO.
GATE:
Gate connects to the external N channel MOSFET gate. GATE is driven positive with respect to A by a driver operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when the fast turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. The turn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating. The gate connection should be kept low impedance to maximize turn-off current.
GND:
This is the input supply reference. GND should have a low impedance connection to the ground plane. It carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also carries significant charge pump currents. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TPS2410 TPS2411 Document Outline FEATURES APPLICATIONS DESCRIPTION ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS: TPS2410/11 DETAILED DESCRIPTION TYPICAL CHARACTERISTICS APPLICATION INFORMATION OVERVIEW TPS2410 vs TPS2411 – MOSFET CONTROL METHODS N+1 POWER SUPPLY – TYPICAL CONNECTION INPUT ORing – TYPICAL CONNECTION SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS RECOMMENDED OPERATING RANGE TPS2410 REGULATION-LOOP STABILITY MOSFET SELECTION AND R(RSET) GATE DRIVE, CHARGE PUMP AND C(BYP) FAST COMPARATOR INPUT FILTERING – C(FLTR) UV, OV, AND PG VDD, BYP, and POWERING OPTIONS INPUT ORing AND STAT BIDIRECTIONAL BLOCKING AND PROTECTION OF C ORing EXAMPLES SUMMARIZED DESIGN PROCEDURE Layout Considerations